TMS320DM642开发之Bug1-Memory map error：READ access by cpu to address 0x1b3f018（Device Config Space）which is not supported in simulator

load程序到DM642开发板上之后，点击了run按钮出现了如下的错误：

Memory map error：READ access by cpu to address 0x1b3f018（Device Config Space）which is not supported in simulator

我检查了CMD文件应该是没有问题的，CMD代码内容如下：

 /*
  * Copyright (C) 2004 SEED Incorporated
  * All Rights Reserved
  */
 /*
  *---------timer1.cmd---------
  *
  */
 -l.\lib\cslDM642.lib
 -l.\lib\rts6400.lib
 MEMORY
 {
   L2 : o = 00000400h l = 0003fb00h  /* all SRAM ，L2,为DSP片内存储器，是第2级存储器
   [第一级存储器包括独立的程序Cach(L1P)和数据Cach(L1D) ],它是一个统一的空间，
   部分程序和数据，统称为L2,可以作为普通的SRAM映射到存储空间              */
   CE01: o = 80000000h l = 00100000h /* external memory   */
   CE02: o = 80100000h l = 00f000000h /* external memory   */
 }

 SECTIONS
 {
     .cinit      >       L2  /*初始化变量和常数表*/
     .text       >       L2  /*可执行代码段的映射*/
     .stack      >       L2  /*为系统堆栈分配存储器。该段用于将变量传递至函数或者用来分配局部变量*/
     .bss        >       L2  /*保留全局和静态变量空间。在启动和导入的时候，C/C++编译器会
                                会启动程序将.cint段中的数据复制出来，以初始化.bss段中的变量*/
     .const      >       L2   /*包含由C/C++限定词const定义的字符常量和数据*/
     .data       >       L2   /*初始化数据段*/
     .far        >       L2   /*供外部文件调用的变量*/
     .switch     >       L2   /*控制语句段映射*/
     .sysmem     >       L2   /*初始化系统空间*/
     .tables     >       L2   /*初始化数据表*/
     .cio        >       L2   /*io口*/
     .capChaAYSpace>    CE01
     .capChaACbSpace>   CE01
    /* .capChaACbSpace>   L2*/
     /* .capChaACrSpace>   L2*/
    .capChaACrSpace>   CE01
     .disChaAYSpace>    CE02
     .disChaACbSpace>   CE02
     .disChaACrSpace>   CE02
     .external   >      CE02     /*外部变量的初始化*/
 }  

这个配置应该是没有问题的，接下来我查看了工程里面的GEL文件，文件内容如下：

 /*--------------------------------------------------------------*/
 /* EVMDM642.gel                                                 */
 /* Version 1.70                                                 */
 /*                                                              */
 /* This GEL file is designed to be used in conjunction with     */
 /* CCS 2.20.18 and the TMS320DM642 based EVM.                   */
 /*                                                              */
 /*--------------------------------------------------------------*/

 /*--------------------------------------------------------------*/
 /* The StartUp() function is called each time CCS is started.   */
 /* Customize this function to perform desired initialization.   */
 /*--------------------------------------------------------------*/

 StartUp()
 {
     setup_memory_map();
     GEL_Reset();
     init_emif();
 } 

 /*--------------------------------------------------------------*/
 /* Setup memory map for DM642 EVM.                              */
 /*                                                              */
 /*--------------------------------------------------------------*/
 setup_memory_map()
 {

     GEL_MapOn();
     GEL_MapReset();

     /* On-chip memory map */
     GEL_MapAdd(0x00000000, , 0x00040000, , ); /* Internal Memory       */
     GEL_MapAdd(0x01800000, , 0x00000058, , ); /* EMIFA CTL REGS        */
     GEL_MapAdd(0x01840000, , 0x000082FC, , ); /* INT MEM CTL REGS      */
     GEL_MapAdd(0x018C0000, , 0x0000003C, , ); /* MCBSP0 CTL REGS       */
     GEL_MapAdd(0x01900000, , 0x0000003C, , ); /* MCBSP1 CTL REGS       */
     GEL_MapAdd(0x01940000, , 0x00000008, , ); /* TIMER0 CTL REGS       */
     GEL_MapAdd(0x01980000, , 0x00000008, , ); /* TIMER1 CTL REGS       */
     GEL_MapAdd(0x019C0000, , 0x00000008, , ); /* INT CTL REGS          */
     GEL_MapAdd(0x01A00000, , 0x0000FFFC, , ); /* EDMA REGS AND PARAM   */
     GEL_MapAdd(0x01A40000, , 0x0000003C, , ); /* MCBSP2 CTL REGS       */
     GEL_MapAdd(0x01A80000, , 0x00000058, , ); /* EMIFB CTL REGS        */
     GEL_MapAdd(0x01AC0000, , 0x00000008, , ); /* TIMER2 CTL REGS       */
     GEL_MapAdd(0x01B00000, , 0x00000024, , ); /* GPIO REGS             */
     GEL_MapAdd(0x01B3F000, , 0x00000020, , ); /* Device Configuration  */
     GEL_MapAdd(0x01B40000, , 0x0000003C, , ); /* I2C CTL REGS          */
     GEL_MapAdd(0x01B4C000, , 0x000002A0, , ); /* McASP0 CTL REGS       */
     GEL_MapAdd(0x01C00000, , 0x00000028, , ); /* PCI CTL REGS          */
     GEL_MapAdd(0x01C20000, , 0x0000000C, , ); /* PCI EEPROM REGS       */
     GEL_MapAdd(0x01C40000, , 0x00000270, , ); /* VP0 Control           */
     GEL_MapAdd(0x01C44000, , 0x00000270, , ); /* VP1 Control           */
     GEL_MapAdd(0x01C48000, , 0x00000270, , ); /* VP2 Control           */
     GEL_MapAdd(0x01C80000, , 0x00000680, , ); /* EMAC CTL REGS         */
     GEL_MapAdd(0x01C81000, , 0x00002000, , ); /* EMAC Wrapper          */
     GEL_MapAdd(0x01C83000, , 0x0000000C, , ); /* EWRAP REGS            */
     GEL_MapAdd(0x01C83800, , 0x00000090, , ); /* MDIO CTL REGS         */
     GEL_MapAdd(0x02000000, , 0x00000030, , ); /* QDMA REGS             */
     GEL_MapAdd(0x30000000, , 0x04000000, , ); /* MCBSP0 Data, EDMA map */
     GEL_MapAdd(0x34000000, , 0x04000000, , ); /* MCBSP1 Data, EDMA map */
     GEL_MapAdd(0x74000000, , 0x02000000, , ); /* VP0 Channel A Data    */
     GEL_MapAdd(0x76000000, , 0x02000000, , ); /* VP0 Channel B Data    */
     GEL_MapAdd(0x78000000, , 0x02000000, , ); /* VP1 Channel A Data    */
     GEL_MapAdd(0x7A000000, , 0x02000000, , ); /* VP1 Channel B Data    */
     GEL_MapAdd(0x7C000000, , 0x02000000, , ); /* VP2 Channel A Data    */
     GEL_MapAdd(0x7E000000, , 0x02000000, , ); /* VP2 Channel B Data    */

     /* Off-chip memory map */
     GEL_MapAdd(0x80000000, , 0x02000000, , ); /* 32MB SDRAM EMIF-A, CE0*/
     GEL_MapAdd(0x90000000, , 0x00080000, , ); /* 4MB Flash EMIF-A, CE1 */
     GEL_MapAdd(0x90080000, , 0x00080000, , ); /* 4MB FPGA EMIF-A, CE1  */
     GEL_MapAdd(0xA0000000, , 0x10000000, , ); /* EMIF-A, CE2 EXPANSION */
     GEL_MapAdd(0xB0000000, , 0x10000000, , ); /* EMIF-A, CE3 EXPANSION */
 }

 /*--------------------------------------------------------------*/
 /* init_emif()                                                     */
 /*--------------------------------------------------------------*/
 init_emif()
 {

 #define EMIFA_GCTL       0x01800000
 #define EMIFA_CE1        0x01800004
 #define EMIFA_CE0        0x01800008
 #define EMIFA_CE2        0x01800010
 #define EMIFA_CE3        0x01800014
 #define EMIFA_SDRAMCTL   0x01800018
 #define EMIFA_SDRAMTIM   0x0180001c
 #define EMIFA_SDRAMEXT   0x01800020
 #define EMIFA_CE1SECCTL  0x01800044
 #define EMIFA_CE0SECCTL  0x01800048
 #define EMIFA_CE2SECCTL  0x01800050
 #define EMIFA_CE3SECCTL  0x01800054

     /* EMIFA */
     *(int *)EMIFA_GCTL     = 0x00052078;
     *(int *)EMIFA_CE0      = 0xffffffd3;  /* CE0 SDRAM                     */
     *(int *)EMIFA_CE1      = 0x73a28e01;  /* CE1 Flash + CPLD              */
     *(int *)EMIFA_CE2      = 0x22a28a22;  /* CE2 Daughtercard 32-bit async */
     *(int *)EMIFA_CE3      = 0x22a28a42;  /* CE3 Daughtercard 32-bit sync  */
     *(int *)EMIFA_SDRAMCTL = 0x57115000;  /* SDRAM control                 */
     *(int *)EMIFA_SDRAMTIM = 0x0000081b;  /* SDRAM timing (refresh)        */
     *(int *)EMIFA_SDRAMEXT = 0x001faf4d;  /* SDRAM extended control        */
     *(int *)EMIFA_CE0SECCTL= 0x00000002;  /* CE0 Secondary Control Reg.    */
     *(int *)EMIFA_CE1SECCTL= 0x00000002;  /* CE1 Secondary Control Reg.    */
     *(int *)EMIFA_CE2SECCTL= 0x00000002;  /* CE2 Secondary Control Reg.    */
     *(int *)EMIFA_CE3SECCTL= 0x00000073;  /* CE3 Secondary Control Reg.    */
 }

 /*--------------------------------------------------------------*/
 /* clear_memory_map()                                           */
 /*--------------------------------------------------------------*/
 clear_memory_map()
 {
     GEL_MapOff();
 }

 /*--------------------------------------------------------------*/
 /* FlushCache()                                                 */
 /*--------------------------------------------------------------*/
 FlushCache()
 {
     /* Invalidate L1I and L1D */
     *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);

     /* Clean L2 */
     *(int *)0x01845004 = 0x1;
 }   

 /*--------------------------------------------------------------*/
 /* OnReset()                                                    */
 /*--------------------------------------------------------------*/
 OnReset(int nErrorCode)
 {
     init_emif();
 }

 /*--------------------------------------------------------------*/
 /* OnPreFileLoaded()                                            */
 /* This function is called automatically when the 'Load Program'*/
 /* Menu item is selected.                                       */
 /*--------------------------------------------------------------*/
 OnPreFileLoaded()
 {
 /*    GEL_Reset();      -- Commented out for CCS 2.20 */
     FlushCache();
     IER = ;
     IFR = ;
     init_emif();
 }

 /*--------------------------------------------------------------*/
 /* OnRestart()                                                  */
 /* This function is called by CCS when you do Debug->Restart.   */
 /* The goal is to put the C6x into a known good state with      */
 /* respect to cache, edma and interrupts.                       */
 /* Failure to do this can cause problems when you restart and   */
 /* run your application code multiple times.  This is different */
 /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
 /* C6x into a known good state.                                 */
 /*--------------------------------------------------------------*/
 OnRestart(int nErrorCode )
 {
       /* Turn off L2 for all EMIFA CE spaces.  App should
       *  manage these for coherancy in the application.
       *  GEL_TextOut("Turn off cache segment\n");
       */
       *(int *)0x1848200 = ;  /* MAR0 */
       *(int *)0x1848204 = ;  /* MAR1 */
       *(int *)0x1848208 = ;  /* MAR2 */
       *(int *)0x184820c = ;  /* MAR3 */

       /* Disable EDMA events and interrupts and clear any
       *  pending events.
       *  GEL_TextOut("Disable EDMA event\n");
       */
       *(int *)0x01A0FFA8 = ;          /* CIERH */
       *(int *)0x01A0FFB4 = ;          /* EERH */
       *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */

       *(int *)0x01A0FFE8 = ;          /* CIERL */
       *(int *)0x01A0FFF4 = ;          /* EERL */
       *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */

       /* Disable other interrupts */
       IER = ;
       IFR = ;
 }    

 /*--------------------------------------------------------------*/
 /* RESET MENU                                                   */
 /*--------------------------------------------------------------*/
 menuitem "Resets";

 hotmenu Reset_BreakPts_and_EMIF()
 {
     GEL_BreakPtReset();
     GEL_Reset();
     init_emif();
 } 

 hotmenu Flush_Cache()
 {
     FlushCache();
 } 

 /*--------------------------------------------------------------*/
 /* MEMORY MAP MENU                                              */
 /*--------------------------------------------------------------*/
 menuitem "Memory Map";

 hotmenu SetMemoryMap()
 {
     setup_memory_map();
 }

 hotmenu ClearMemoryMap()
 {
     clear_memory_map();
 }

 /*--------------------------------------------------------------*/
 /* BOARD OPTIONS MENU                                           */
 /*--------------------------------------------------------------*/
 menuitem "Board Options";

 #define CPLD_REVISION 0x9008001F

 hotmenu CheckFPGARevision()
 {
     GEL_TextOut(" FPGA Revision %d\n","Output",,,, *(char *)CPLD_REVISION);
     GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on (DS9)\n","Output",,,);
 }

我的硬件的配置时 CCS3.3+SEED-DKT-VPM642+SEED-XDS560PLUS Emulator
下面是工程run过程的Message：

解决办法：

已经解决了：问题如下

1.我在CCS3.3启动的Parallel Debug Manager里面选择出了问题：

在这里我们需要选择的是C64xx XDS560 Emulator所连接的CPU_1，而不是上面的DM642 Device Functional Simulator 所连接的DM642的 模拟核，当我选择第一个Simulator的选项并打开导入工程之后建立的就是DM642的软件仿真程序而不是硬件仿真！（这个状态我们也很清楚的在CCS3.3的最上面的图表中看到为：DM642 Device Functional Simulator。所以这也是我还未能很好的使用CCS这款软件导致的。）

当我们点击编译Compile+建立Build+加载load Program+Run时出现的错误，程序被加载到了虚拟核中，但是在虚拟核上仿真DM642并不支持，所以就会出现上面的错误！

2.当我弄清楚这个问题之后，我打开了下面的Emulator的CPU_1的工程，按步骤加载并运行了程序，发现还是没能在显示器上得到我要的视频数据，后面检查了半天发现是BNC的视频输出线存在接触不良的情况导致的~（真是机缘巧合找到的原因，所以说大家也要多多注意这种硬件的问题吧！）