VHDL之package
Pacakge
Frequently used pieces of VHDL code are usually written in the form of COMPONENTS, FUNCTIONS, or PROCEDURES. Such codes are then placed inside a PACKAGE and compiled into the destination LIBRARY.

1 Syntax
Besides COMPONENTS, FUNCTIONS, and PROCEDURES, it can also contain TYPE and CONSTANT definitions, among others. Its syntax is presented below.
PACKAGE package_name IS
(declarations)
END package_name; [PACKAGE BODY package_name IS
(FUNCTION and PROCEDURE descriptions)
END package_name;]
2 Simple Package
It shows a PACKAGE called my_package. It contains only TYPE and CONSTANT declarations, so a PACKAGE BODY is not necessary.
------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------
PACKAGE my_package IS
TYPE state IS (st1, st2, st3, st4);
TYPE color IS (red, green, blue);
CONSTANT vec: STD_LOGIC_VECTOR( DOWNTO ) := "";
END my_package;
------------------------------------------------
The PACKAGE above can now be compiled, becoming then part of our work LIBRARY (or any other). To make use of it in a VHDL code, we have to add a new USE clause to the main code (USE work.my_package.all), as shown below.
------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
------------------------------------
ENTITY...
...
ARCHITECTURE...
...
------------------------------------
3 Package in ASIC
In ASIC design, use ieee.std_logic_1164, and ieee.numeric_std, NEVER use ieee.std_logic_arith
numeric_std defines numeric types and arithmetic functions for use with synthesis tools.
- two numeric types are defined: UNSIGNED, SIGNED (represents a SIGNED number in vector form)
- base element type is type STD_LOGIC. The leftmost bit is treated as the most significant bit.
- signed vectors are represented in two's complement form.
- contains overloaded arithmetic operators on the SIGNED and UNSIGNED types.
- contains useful type conversions functions.
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