understanding of Pipe line & Timing Logic

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module vlg_add(
input clk,
output [7:0]a,
output [7:0]b,
output [7:0]c,
output [7:0]d
);
 
reg [7:0]reg_a = 0;
always@(posedge clk)
begin
    reg_a <= reg_a + 8'd1;
end

reg [7:0]reg_b = 0;
always@(posedge clk)
begin
    reg_b <= reg_a + 8'd2;
end

reg [7:0]reg_c = 0;
always@(posedge clk)
begin
    reg_c <= reg_b + 8'd3;
end

reg [7:0]reg_d = 0;
always@(posedge clk)
begin
    reg_d <= reg_c + 8'd4;
end

assign a = reg_a;
assign b = reg_b;
assign c = reg_c;
assign d = reg_d;  
 
endmodule
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////////////////// TestBench//////////////////////////////////////////////////////////////

`timescale 1 ns / 1 ps
module my_sim_vlg_tst();
 
reg clk;
wire [7:0]a;
wire [7:0]b;
wire [7:0]c;
wire [7:0]d;

vlg_add vlg_add_inst(
  .clk(clk),
  .a(a),
  .b(b),
  .c(c),
  .d(d)
);

initial
begin
  clk = 0;
  forever #10 clk = ~clk;
end

endmodule

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