Verilog实现IIC通讯第二版

HMC5883三轴磁力传感器IIC通讯模块的VerilogHDL的实现

上一版并没有实现我想要的功能

0.0.1版正在修订中 2013/9/2

 //date :2013/7/7

    //designer :pengxiaoen

    //synthesizer:QuartusII 12.1

    //function : IIC实现HMC5883的通讯  50M /(400k × 4)= 32

  `define WriteAddress  'h3c

  `define ReadAddress   'h3d

 `define RegAAddress   'h00  //配置寄存器A

 `define RegBAddress   'h01  //配置寄存器B

 `define ModelAddress  'h02  //模式寄存器

 `define X_MSBAddress  'h03  //X MSB寄存器

 `define X_LSBAddress  'h04

 `define Z_MSBAddress  'h05

 `define Z_LSBAddress  'h06

 `define Y_MSBAddress  'h07

 `define Y_LSBAddress  'h08

 `define STATEAddress  'h09  //状态寄存器

 `define IdentifyAAddress  'h10  //识别寄存器A

 `define IdentifyBAddress  'h10

 `define IdentifyCAddress  'h10

 `define INITIAL

 `define DELAY

 `define MEASURE  

 `define START

 `define Re

 `define Se

 `define STOP   

   //`default_nettype none

   module HMC5883_2 (

                       clock,reset,

                             sda,scl,

                             out_seg,

                             sel_seg,

                                      IIC_result

                             );

   input clock,reset;

   inout sda,scl;

   output reg [:]out_seg;

   output reg IIC_result;

   output reg [:]sel_seg;

   reg [:] SEND_buffer;

   reg [:] Re_buffer ;

   reg sda_reg;

   reg scl_reg;

   reg ack_reg;

   reg sda_enable;

   reg scl_enable;

   reg IC_state;

   reg n_IC_state;

   reg [:]state;           //当前状态寄存器

   reg state_finish_flag ;   //

   reg [:] scl_4;

   reg [:] step_counter;

   reg [:] clk_temp ;

 //==============================================================================================

 //-------------时钟控制模块------------------start---------------

   always @ (posedge clock or negedge reset)

   if (!reset)

       begin

            clk_temp <= 'd0;

             scl_4 <= 'd0;

        end

   else if (clk_temp=='d15)

            begin

                clk_temp <= 'd0;

                if (state_finish_flag) scl_4 <= 'd0;

                else if (scl_4 == 'b111_111)   //这里是一个保护机制，可以设置一个flag

                       scl_4 <= 'b111_111;

                     else  scl_4 <= scl_4 + ;

           end

        else clk_temp <= clk_temp + ;

 //----------时钟控制模块----------end-----------

 //--------一个检测的pin---------start-----------

 always @(posedge clock or negedge reset)

 if(!reset)

    IIC_result <= 'd0;

 else if(scl_4 == 'b111_111)

        IIC_result <= 'd1;

         else ;

 //-----------一个检测的pin-------end----------        

 //-------延时模块----5us------start--------

  reg [:] delay_counter;

  reg delay_enable;

  always @(posedge clock )

   if(!delay_enable)

       begin

            delay_counter <= 'd0;

            state_finish_flag <= 'd0;

       end

   else  if(delay_counter == 'd250)

            begin

                state_finish_flag <= 'd1;

                delay_counter <= 'd0;

            end

         else  begin

                     delay_counter <= delay_counter + ;

                         state_finish_flag <= 'd0;

                   end

  //--------------延时模块-------end---------------

  //----------状态机控制模块---------start-------

  always @ (posedge clock or negedge reset)

  if(!reset)

    IC_state <= `INITIAL;

   else IC_state <= n_IC_state;             

  //------------------------------------------

   always @ (posedge state_finish_flag or negedge reset)

   if (!reset)

       begin

            SEND_buffer  <= 'd0;

            n_IC_state   <= 'd0;

        end

    else if(IC_state == `INITIAL)

       case (step_counter)

              : begin  state <= `START;end

              : begin  state <= `Se;  SEND_buffer <= `WriteAddress;   end

              : begin  state <= `Se;  SEND_buffer <= `ModelAddress;   end

              : begin  state <= `Se;  SEND_buffer <= `RegAAddress;   end

              : begin  state <= `STOP;   end

                  : begin  n_IC_state <= `MEASURE;   end

              default state <= `START;

        endcase

   else if (IC_state == `MEASURE)

       case (step_counter)

               : begin  state <= `START; end

               : begin  state <= `Se;   SEND_buffer <= `WriteAddress; end

               : begin  state <= `Se;   SEND_buffer <= `X_MSBAddress; end

               : begin  state <= `START; end

               : begin  state <= `Se;   SEND_buffer <= `ReadAddress;end

               : begin  state <= `Re;   end

               : begin  state <= `Re;   end

               : begin  state <= `Re;   end

               : begin  state <= `Re;   end

               : begin  state <= `Re;   end

              : begin  state <= `Re;   end

              : begin  state <= `STOP; end

                  :begin  n_IC_state <= `INITIAL;  end

              default state <= `START;

        endcase

        else ;

  //----------状态机控制模块----------end--- ---

 //----------执行步骤计数--------start------------

 always @ (posedge clock  or negedge reset)

 if (!reset) begin

     step_counter <= 'd0;  end

 else  if((IC_state == `INITIAL)&& (state_finish_flag))   begin

              if(step_counter == 'd5)  step_counter <= 4'd0;

                 else step_counter <= step_counter + ; end

        else if((IC_state == `MEASURE) && (state_finish_flag))   begin

                  if(step_counter == 'd12 ) step_counter <= 4'd0;

                   else step_counter <= step_counter + ;     end

                  else ;

 //----------执行步骤计数--------end------------ 

  //-----------外部数据线 控制模块----start------

  always @ (posedge clock or negedge reset)

 if(!reset)

   begin

        Re_buffer <= 'd0;

          sda_enable <= 'd0;

          scl_enable <= 'd0;

          delay_enable <= 'd0;

   end

  else case (state)

      `START : case (scl_4)

                  : begin sda_enable <= 'd1; scl_enable <= 1'd1; delay_enable <= 'd0;

                                   sda_reg <= 'd1;  scl_reg <= 1'd0;  end

                  : begin sda_reg <= 'd1;  scl_reg <= 1'd0;  end

                  : begin sda_reg <= 'd1;  scl_reg <= 1'd1;  end

                  : begin sda_reg <= 'd0;  scl_reg <= 1'd1;  end

                       : delay_enable <= 'd1;

                   default  begin sda_reg <= 'dz;  scl_reg <= 1'dz;  end

               endcase

      `STOP  : case (scl_4)

                  : begin sda_enable <= 'd1; scl_enable <= 1'd1; delay_enable <= 'd0;

                                sda_reg <= 'd0;  scl_reg <= 1'd0; end

                  : begin sda_reg <= 'd0;  scl_reg <= 1'd0; end

                  : begin sda_reg <= 'd0;  scl_reg <= 1'd1; end

                  : begin sda_reg <= 'd1;  scl_reg <= 1'd1; end

                       : delay_enable <= 'd1;

                   default  begin sda_reg <= 'dz;  scl_reg <= 1'dz; end

                endcase

       `Se    : case (scl_4)

                  : begin sda_enable <= 'd1; scl_enable <= 1'd1; delay_enable <= 'd0;

                                sda_reg <= 'd0;            scl_reg <= 1'd0;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                  : begin                             scl_reg <= 'd0;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                  : begin                             scl_reg <= 'd0;  end

                  : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin                             scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin                             scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin                             scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin                             scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin                             scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd0;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 : begin sda_reg <= SEND_buffer[];  scl_reg <= 'd1;  end

                 //此时序之后必须释放掉sda控制权  等待响应

                 : begin  sda_enable <= 'd0; scl_enable <= 1'd0; delay_enable <= 'd1;

                                 ack_reg <= 'd0;           scl_reg <= 1'd0;  end //这里出现了一个警告，因为ack_reg没有利用到

                 : begin  ack_reg <= sda;            scl_reg <= 'd0;  end

                      : begin  ack_reg <= sda;            scl_reg <= 'd1;  end

                 : begin  ack_reg <= sda;            scl_reg <= 'd1;  end

                //此时IC有可能在一个时钟下来不及响应，从而导致主机没有接收到响应信号

                 default  begin                        scl_reg <= 'dz;      end

              endcase  

       `Re  : case (scl_4)

                      : begin  sda_enable <= 'd0; scl_enable <= 1'd1; delay_enable <= 'd0;

                                                        scl_reg <= 'd0;  end

                      : begin                        scl_reg <= 'd0;  end

                      : begin                        scl_reg <= 'd1;  end

                      : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                      : begin                        scl_reg <= 'd0;  end

                      : begin                        scl_reg <= 'd0;  end

                      : begin                        scl_reg <= 'd1;  end

                      : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                      : begin                        scl_reg <= 'd0;  end

                      : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd0;  end

                     : begin                        scl_reg <= 'd1;  end

                     : begin Re_buffer[] <= sda;   scl_reg <= 'd1;  end

                //此时序之后主机夺回sda控制权,延时开始

                     : begin sda_enable <= 'd1; delay_enable <= 1'd1;

                                sda_reg <= ; scl_reg <= 'd0;  end

                     : begin  sda_reg <= ; scl_reg <= 'd0;  end

                     : begin  sda_reg <= ; scl_reg <= 'd1;  end

                     : begin  sda_reg <= ; scl_reg <= 'd1;  end

                     default  begin sda_reg <= 'dz;    scl_reg <= 1'dz;end

                endcase

       endcase

  //-------外部数据线 控制模块----------end---------------

  assign sda = sda_enable ? sda_reg : 'dz ;

  assign scl = scl_enable ? scl_reg : 'dz ;

 //==================================================================================== 

  //--------------数码管显示部分=======只显示了一部分，有待优化============================

  always @ ( posedge clock or negedge reset)

  if (!reset)

    begin

      sel_seg <= 'b111110;

    end

  else if(state_finish_flag)

         begin

           sel_seg <= {sel_seg[:],sel_seg[]};

         end

  //------------------------------------------------

  always @(posedge clock or negedge reset)

  if (!reset) out_seg <= 'd0;

  else

    begin

      case (Re_buffer[:])  //刚开始这里没有[3：0] 居然没有报错，连个警告都没有，这是为什么呢

          'b0000  :  out_seg<=8'b1100_0000;//0000_0011

          'b0001  :  out_seg<=8'b1111_1001;//1001_1111

          'b0010  :  out_seg<=8'b1010_0100;//0010_0101

          'b0011  :  out_seg<=8'b1011_0000;//0000_1101

          'b0100  :  out_seg<=8'b1001_1001;//1001_1001

          'b0101  :  out_seg<=8'b1001_0010;//0100_1001

          'b0110  :  out_seg<=8'b1000_0010;//0100_0001

          'b0111  :  out_seg<=8'b1111_1000;//0001_1111

          'b1000  :  out_seg<=8'b1000_0000;//0000_0001

          'b1001  :  out_seg<=8'b1001_1000;//0001_1001

          'b1010  :  out_seg<=8'b1000_1000;//0001_0001

          'b1011  :  out_seg<=8'b1000_0011;//1100_0001

          'b1100  :  out_seg<=8'b1100_0110;//0110_0011

          'b1101  :  out_seg<=8'b1010_0001;//1000_0101

          'b1110  :  out_seg<=8'b1000_0110;//0110_0001

          'b1111  :  out_seg<=8'b1000_1110;//0111_0001

       endcase

    end

 //-------------------------------================================= 

  endmodule

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