带控制端的逻辑运算电路_分别完成正整数的平方、立方和阶乘的运算verilog语言

练习：设计一个带控制端的逻辑运算电路，分别完成正整数的平方、立方和阶乘的运算。

//--------------myfunction----------

modulemyfunction(clk,n,result,reset,sl);

output[6:0]result;

input[2:0] n;

input reset,clk;

input [1:0] sl;

reg[6:0]result;//define input and output

always @(posedgeclk)

begin

if(!reset)

result<=0;

else

begin

case(sl)

2'd0:result<=square(n);

2'd1:result<=cubic(n);

2'd2:result<=factorial(n);

endcase

end

end

function[6:0]square;

input [2:0]operand;

begin

square=operand*operand;

end

endfunction

function[6:0]cubic;

input [2:0]operand;

begin

cubic=operand*operand*operand;

end

endfunction

function[6:0]factorial;

input [2:0]operand;

reg [2:0] index;

begin

factorial = 1 ;

for(index = 2; index <= operand; index =index + 1)

factorial = index * factorial;

end

endfunction

endmodule

//--------------testmyfunc----------

`include"./myfunction.v"

`timescale1ns/100ps

`define clk_cycle50

module testmyfunc;

reg[2:0] n;

reg reset,clk;

reg[1:0] sl;

wire[6:0] result;

parametertimes=20;

initial

begin

n=0;

reset=1;

clk=0;

sl=0;

#100 reset=0;

#100 reset=1;

repeat(times)

begin

#50sl={$random}%3;

#50 n={$random}%6;

end

#1000 $stop;

end

always #`clk_cycleclk=~clk;

myfunctionmyfunct(.clk(clk),.n(n),.result(result),.reset(reset),.sl(sl));

endmodule