Basys3在线调试视频指南及代码

fpga在线调试视频链接

FPGA选择型号:xc7a35tcpg236-1

des文件

`timescale 1ns / 1ps

module top(
        output [1:0] led,
        output [1:0] led_btn,
        input clk,
        output clk_out_5m,
        output clk_out_20m,
        wire locked,
        //input btn_1,
        wire reset
        );

      //  reg [1:0]  led_r = 2'b01;
     //(* keep ="TRUE" *)reg [1:0]  led_r = 2'b01;

     (* MARK_DEBUG="true" *) reg [1:0]  led_r = 2'b01;
     reg [1:0]  led_btn_r = 2'b01;

     assign led = led_r;
     assign led_btn = led_btn_r;

       clk_wiz_0 instance_name
      (
      // Clock in ports
       .clk_in(clk),      // input clk_in
       // Clock out ports
       .clk_out_5m(clk_out_5m),     // output clk_out_5m
       .clk_out_200m(clk_out_200m),     // output clk_out_200m
       // Status and control signals
       .reset(reset), // input reset
       .locked(locked)); 

    ila_0 ila_inst_1 (
        .clk(clk), // input wire clk
        .probe0(led_r) // input wire [1:0] probe0
    );

    parameter TIM = 5000000;
    reg[31:0] counter;
    always@(posedge clk_out_5m)
    begin
        counter <= counter + 1;
        if(counter == TIM)
        begin
            counter <= 0;
            if(led_r == 2'b01)  led_r <= 2'b10;
            else                led_r <= 2'b01;
        end
    end

//    always@(negedge btn_1)
//    begin
//        if(led_btn_r == 2'b01)   led_btn_r <= 2'b10;
//        else                     led_btn_r <= 2'b01;
//    end

//    always@(negedge btn_1)
//    begin
//        if(led_btn_r == 2'b01)   led_btn_r <= 2'b10;
//        else                     led_btn_r <= 2'b01;
//    end

endmodule

xdc文件

set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led_btn[0]}]
set_property PACKAGE_PIN V19 [get_ports {led_btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_btn[0]}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN T17 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]

#set_property IOSTANDARD LVCMOS33 [get_ports btn_1]
#set_property PACKAGE_PIN T18 [get_ports btn_1]

set_property PACKAGE_PIN J1 [get_ports clk_out_5m]
set_property PACKAGE_PIN L2 [get_ports clk_out_20m]
set_property PACKAGE_PIN J2 [get_ports locked]
set_property IOSTANDARD LVCMOS33 [get_ports clk_out_5m]
set_property IOSTANDARD LVCMOS33 [get_ports clk_out_20m]
set_property IOSTANDARD LVCMOS33 [get_ports locked]

connect_debug_port u_ila_0/clk [get_nets [list clk_IBUF_BUFG]]
connect_debug_port dbg_hub/clk [get_nets clk_IBUF_BUFG]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list instance_name/inst/clk_out_5m]]
set_property port_width 2 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {led_r[0]} {led_r[1]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_BUFG]