异步时钟FIFO（一）

FIFO一般用于通过两个不同时钟域的数据传输。一个水池有进和出两个通道，由于进出口水流不一致所以需要水池加以缓冲。堆栈也是相当于水池的作用。如果输入端不是连续的数据流，可以通过堆栈来调节使数据以稳定的状态输出。如果数据的输入时钟大于输出，那么总有一个时间使堆栈溢出则溢出的这部分会被舍弃。一般异步时钟需要同步，本文只是基于FIFO的基本原理编程。后续会对FIFO进行技术上的改进。

代码：

 module FIFIO(input clkin,input write,input [:] datain,input clkout,input read,output reg [:]  dataout,output reg empty,output reg full);
 reg [:]stack[:];
 reg [:]data_in_point=;
 reg [:] data_in_count=;
 reg [:]data_out_point=;
 reg  data_in_num=;
 reg data_out_num=;
 always@(posedge clkin)
 begin     

                         case(data_in_num)
                             :if(write) begin if((data_in_count-data_out_point)>'h3fff) begin full<=1;data_in_num<=0;end else begin data_in_point<=data_in_count[9:0];data_in_num<=1;full<=0;end end
                             :begin stack[data_in_point]<=datain;data_in_count<=data_in_count+;data_in_num<=;end
                          endcase

 end
 always@(posedge clkout)
 begin 

                     case(data_out_num)
                         :if(read) begin if((data_in_count-data_out_point)==) begin empty<=;data_out_num<=;end else begin empty<=;data_out_num<=;end end
                         :begin dataout<=stack[data_out_point];data_out_num<=;if(data_out_point=='h3fff)data_out_point<=0;else data_out_point<=data_out_point+1; end
                      endcase

 end 

 endmodule

验证代码：

 module fifibench();
 reg clkin,clkout;
 reg write,read;
 wire empty,full;
 wire [:]dataout;
 reg [:] datain;
 FIFIO M0 (.clkin(clkin),.write(write),.datain(datain),.clkout(clkout),.read(read),.dataout(dataout),.empty(empty),.full(full));
 initial begin  clkin=;clkout=;write=;read=;datain=;end
 always begin # clkin=!clkin;end
 always begin # clkout=!clkout;end
 always begin # write=!write;end
 always begin # read=!read;end
 always begin # datain=datain+; end
 initial # $stop;
 endmodule