BT1120时序，可以用于自测用

    module bt1120_gen #(
        parameter H_SYNC                 =  ,
        parameter H_FRONT_PORCH =  ,
        parameter H_BACK_PORCH  = ,
        parameter V_SYNC            =   ,
        parameter V_FRONT_PORCH =   ,
        parameter V_BACK_PORCH  =  

    )(
        input             clk,
        input             rst_p,
//        input [5:0] h_sync_pixcels,
//        input [5:0] h_front_porch_pixcels,
//        input [5:0] h_back_porch_pixcels,
//        input [5:0] v_sync_lines,
//        input [5:0] v_front_porch_lines,
//        input [5:0] v_back_porch_lines,

        input [:] col,
        input [:] row,

        output reg[:] odata,
        output reg v_sync,
        output reg h_sync,
        output reg de

    );

    parameter S_H_SYNC = 'b00;
    parameter S_H_BACK_PORCH = 'b01;
    parameter S_H_ACTIVE   = 'b10;
    parameter S_H_FRONT_PORCH = 'b11;
    parameter S_V_SYNC = 'b00;
    parameter S_V_BACK_PORCH = 'b01;
    parameter S_V_ACTIVE   = 'b10;
    parameter S_V_FRONT_PORCH = 'b11;

    reg [:] h_pre_state = S_H_FRONT_PORCH;
    reg [:] h_nx_state = S_H_FRONT_PORCH;
    reg [:] v_pre_state = S_V_SYNC;
    reg [:] v_nx_state = S_V_SYNC;

    reg [:] h_cnt     = ;
    reg [:] v_cnt     = ;
    reg [:] sync_code = ;
    reg           de_r     = 'b0;
    reg             vid_sop_r = 'b0;
    wire            pos_vid_sop;
    reg                fifo_rd_valid = 'b0;
    reg [:] fifo_rd_data_r = 'd0;
    reg [:] sync_code_r = 'd0;
    reg [:] sync_code_r1 = 'd0;
    reg                  de_r1 = 'b0;
    reg                    de_r2 = 'b0;
    reg                    h_sync_r = 'b0;
    reg                    h_sync_r1 = 'b0;
    reg                    h_sync_r2 = 'b0;
    reg                    v_sync_r  = 'b0;
    reg                    v_sync_r1 = 'b0;
    reg                    v_sync_r2 = 'b0;

    reg data_en = 'b0;
    reg data_en_dly = 'b0;
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    data_en <= 'b1;
            else
                    data_en <= 'b0;
    end

    always @( posedge clk )
    begin
            data_en_dly <= data_en;
    end

    always @( posedge clk )
    begin
            if( data_en_dly )
                    fifo_rd_data_r <= fifo_rd_data_r + 'b1;
            else
                    fifo_rd_data_r <= 'd0;
    end

/***********************************************************************

***********************************************************************/    

    always @( posedge clk )//or posedge rst_p
    begin
            if( rst_p ) begin
                h_pre_state <= S_H_FRONT_PORCH;
                v_pre_state <= S_V_SYNC;

            end else begin
                h_pre_state <= h_nx_state;
                v_pre_state <= v_nx_state;
            end
    end

    always @( * )
    begin
            case( h_pre_state )
            S_H_SYNC :
                    if( h_cnt == H_SYNC - )
                            h_nx_state  <= S_H_BACK_PORCH;
                    else
                            h_nx_state <= S_H_SYNC;

            S_H_BACK_PORCH :
            begin
                    if( h_cnt == H_BACK_PORCH - )
                            h_nx_state  <= S_H_ACTIVE;
                    else
                            h_nx_state <= S_H_BACK_PORCH;
            end
            S_H_ACTIVE    :
            begin
                   if( h_cnt == col - )
                        h_nx_state  <= S_H_FRONT_PORCH;
                else
                        h_nx_state <= S_H_ACTIVE;        

            end
            S_H_FRONT_PORCH :
            begin
                if( h_cnt == H_FRONT_PORCH - )
                        h_nx_state  <= S_H_SYNC;
                else
                        h_nx_state <= S_H_FRONT_PORCH;          

            end
            default:;
            endcase    

    end

    always @( * )
    begin
            case( v_pre_state )
            S_V_SYNC :
            begin
                    if( h_nx_state == S_H_FRONT_PORCH &&  h_pre_state  == S_H_ACTIVE   ) begin
                            if( v_cnt == V_SYNC - )
                                    v_nx_state = S_V_BACK_PORCH;
                            else
                                v_nx_state = S_V_SYNC;
                    end else begin
                            v_nx_state = S_V_SYNC;
                    end
            end
            S_V_BACK_PORCH :
            begin
                    if( h_nx_state == S_H_FRONT_PORCH &&  h_pre_state  == S_H_ACTIVE   ) begin
                            if( v_cnt == V_BACK_PORCH - )
                                    v_nx_state = S_V_ACTIVE;
                            else
                                    v_nx_state = S_V_BACK_PORCH;
                    end else begin
                            v_nx_state = S_V_BACK_PORCH;
                    end
            end
            S_V_ACTIVE    :
            begin
                    if( h_nx_state == S_H_FRONT_PORCH &&  h_pre_state  == S_H_ACTIVE   ) begin
                           if( v_cnt == row - )
                                v_nx_state = S_V_FRONT_PORCH;
                            else
                                    v_nx_state = S_V_ACTIVE;
                end else begin
                        v_nx_state = S_V_ACTIVE;
                end       

            end
            S_V_FRONT_PORCH :
            begin
                    if( h_nx_state == S_H_FRONT_PORCH &&  h_pre_state  == S_H_ACTIVE   ) begin
                        if( v_cnt == V_FRONT_PORCH -'b1 )
                                v_nx_state = S_V_SYNC;
                            else
                                    v_nx_state = S_V_FRONT_PORCH;
                    end else begin
                            v_nx_state = S_V_FRONT_PORCH;
                    end
            end
            default:;
            endcase
//            end else begin
//                    v_nx_state = v_nx_state;
//            end
//
    end
/***********************************************************************
cnt
***********************************************************************/
    always @( posedge clk )
    begin
        if( rst_p ) begin
            h_cnt <= ;
        end else begin
            case( h_nx_state )
            S_H_SYNC :
            begin
                     if( h_pre_state == S_H_FRONT_PORCH  )  //&& h_cnt == H_FRONT_PORCH -1
                            h_cnt <= ;
                    else
                            h_cnt <= h_cnt + 'b1;
            end
            S_H_BACK_PORCH :
            begin
                    if( h_pre_state == S_H_SYNC )//&& h_cnt == H_SYNC -1)
                            h_cnt <= ;
                    else
                            h_cnt <= h_cnt + 'b1;
            end
            S_H_ACTIVE    :
            begin
                if( h_pre_state == S_H_BACK_PORCH)// && h_cnt == H_BACK_PORCH -1)
                        h_cnt <= ;
                else
                        h_cnt <= h_cnt + 'b1;
            end
            S_H_FRONT_PORCH :
            begin
                if( h_pre_state == S_H_ACTIVE )//&& h_cnt == col -1)
                        h_cnt <= ;
                else
                        h_cnt <= h_cnt + 'b1;
            end
            default:;
            endcase
    end
    end 

    always @( posedge clk or posedge rst_p )
    begin
        if( rst_p)
            v_cnt <= ;
        else  begin
            if( h_nx_state == S_H_FRONT_PORCH &&  h_pre_state  == S_H_ACTIVE   )
            begin
                case( v_nx_state )
                S_V_SYNC :
                begin
                    if( v_pre_state == S_V_FRONT_PORCH )
                            v_cnt <= ;
                    else
                            v_cnt <= v_cnt + 'b1;
                end

                S_V_BACK_PORCH :
                begin
                    if( v_pre_state  ==  S_V_SYNC )
                            v_cnt <= ;
                    else
                            v_cnt <= v_cnt + 'b1;
                end
                S_V_ACTIVE    :
                begin
                   if( v_pre_state  ==  S_V_BACK_PORCH )
                        v_cnt <= ;
                else
                        v_cnt <= v_cnt + 'b1;        

                end
                S_V_FRONT_PORCH :
                begin
                if( v_pre_state  ==  S_V_ACTIVE )
                        v_cnt <= ;
                else
                        v_cnt <= v_cnt + 'b1;       

                end
                default:;
                endcase
            end
        end
    end

/***********************************************************************
h_sync v_sync de
***********************************************************************/
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_SYNC )
                    h_sync_r <= 'b1;
            else
                    h_sync_r <= 'b0;
    end

    always @( posedge clk )
    begin
            if( v_nx_state == S_V_SYNC )
                    v_sync_r <= 'b1;
            else
                    v_sync_r <= 'b0;
    end

    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    de_r <= 'b1;
            else
                    de_r <= 'b0;
    end
/***********************************************************************

***********************************************************************/    

    always @( posedge clk )
    begin
        if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                sync_code <= 'd0;
        else if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                case( h_cnt )
                        H_BACK_PORCH - : sync_code <= 'habab;//16'hab00;//
                        H_BACK_PORCH - : sync_code <= 'h0000;//16'h00ff;//
                        H_BACK_PORCH - : sync_code <= 'h0000;//16'h8010;//
                        H_BACK_PORCH - : sync_code <= 'hffff;//16'h8010;//
                default:sync_code <= 'h1080;
                endcase
        else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 'hffff;//16'h00ff;//
                else begin
                    case(h_cnt )
                         : sync_code <= 'h0000;//16'hb600;//
                         : sync_code <= 'h0000;//16'h8010;//
                         : sync_code <= 'hb6b6;//16'h8010;//
                    default:sync_code <= 'h1080;
                    endcase
                end
        else if(( h_nx_state == S_H_BACK_PORCH)) begin // && ( v_nx_state == S_V_ACTIVE)
            case(h_cnt )
                      H_BACK_PORCH - : sync_code <= 'h8080;//16'h8000;//
                      H_BACK_PORCH - : sync_code <= 'h0000;//16'h00ff;//
                      H_BACK_PORCH - : sync_code <= 'h0000;//16'h8010;//
                      H_BACK_PORCH - : sync_code <= 'hffff;//16'h8010;//
              default:sync_code <= 'h1080;
              endcase
        end
        else if(( h_nx_state == S_H_FRONT_PORCH)) begin// && ( v_nx_state == S_V_ACTIVE)
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 'hffff;//16'h00ff;//
                else begin
                    case(h_cnt )
                             : sync_code <= 'h0000;//16'h9d00;//
                             : sync_code <= 'h0000;//16'h8010;//
                             : sync_code <= 'h9d9d;//16'h8010;//
                    default:sync_code <= 'h1080;
                    endcase
                end
        end
        else begin
                    sync_code <= 'h1080;
        end

    end
/***********************************************************************
sync
***********************************************************************/    

    always @( posedge clk )
    begin
        sync_code_r <= sync_code;
        sync_code_r1<= sync_code_r;
        de_r1 <= de_r;
        de_r2 <= de_r1;
        h_sync_r1 <= h_sync_r;
        h_sync_r2 <= h_sync_r1;
        v_sync_r1 <= v_sync_r;
        v_sync_r2 <= v_sync_r1;

    end
    always @( posedge clk )
    begin
            odata <= sync_code_r1 + fifo_rd_data_r;
            h_sync <= h_sync_r2;
            v_sync <= v_sync_r2;
            de     <= de_r2;
    end

    endmodule