Verilog设计指定寄存器数组在综合时使用block memory资源

自己用verilog代码写的rom或ram会被综合成查找表LUT+REG构建，并没有使用到block memory资源。

资料：https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram.htm

ramstyle Verilog HDL Synthesis Attribute
A Verilog HDL synthesis attribute that controls the way an inferred RAM is implemented.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_ramstyle. This synthesis attribute behaves identically to the ramstyle synthesis attribute.
To use the ramstyle attribute in a Verilog Design File (.v) Definition, specify the synthesis attribute delimited by (* and *) preceding the Variable Declaration of an inferred RAM whose implementation you want to control. Specify the synthesis attribute value as "logic", "no_rw_check", "M9K", "M20K", "M144K", "MLAB", or depending on the type of memory block you want the Quartus Prime software to use when implementing the inferred RAM. If you use the synthesis attribute on anything but a variable that represents a RAM, or if you specify an illegal value, the Quartus Primesoftware ignores that synthesis attribute.

By setting the value to "M4K", "M9K", "M20K", "M144K", or "MLAB", you can choose the type of memory block that the Quartus Prime software uses when implementing the inferred RAM. If the attribute is set to "logic", then the RAM is implemented in logic cells.

In addition to specifying the type of memory block for the RAM implementation, by setting the value to "no_rw_check", you can use the ramstyle attribute to indicate that you do not care about the output of the inferred RAM when there are simultaneous reads and writes to the same address. By default, the Quartus Prime software tries to create an inferred RAM with the same read-during-write behavior as your HDL source. In some cases, a RAM must be mapped into logic because it has a read-during-write behavior that is not supported by the memory blocks in your target device. In other cases, the Quartus Prime software must insert extra logic to mimic your read-during-write behavior, which can increase the resource requirements or reduce the performance of your design. Setting the "no_rw_check" value directs the Quartus Prime Compiler that the read-during-write behavior of the HDL source does not need to be preserved.

Note: You can specify both a block-type and "no_rw_check" in a single attribute by separating the values with a comma, for example "no_rw_check, M144K", or you can specify only a block-type or "no_rw_check".
For example, in the following code, the ramstyle synthesis attribute specifies that the inferred RAM my_ram should be implemented using an :

(* ramstyle = "M144K" *) reg [0:7] my_ram[0:63];
Note: You can also embed the ramstyle synthesis attribute in a comment following the Variable Declaration of an inferred RAM, as shown in the following code:

reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M144K" */;

可以选择板卡上的BLOCK RAM芯片型号，让手写的代码综合为block ram；设置为logic，则综合时会使用逻辑资源LUT+REG实现RAM。

除了为 RAM 实现指定内存块的类型之外，通过将值设置为“ no _ rw _ check”，您可以使用 ramstyle 属性来表明，当对同一地址同时进行读写操作时，您不关心推断出的 RAM 的输出。默认情况下，quartusprime 软件会尝试创建一个具有与您的 HDL 源相同的读写行为的推断 RAM。在某些情况下，RAM 必须映射到逻辑中，因为它具有写入期间的读取行为，而目标设备中的内存块不支持这种行为。在其他情况下，Quartus Prime 软件必须插入额外的逻辑来模拟在写入期间的读取行为，这可能会增加资源需求或降低设计的性能。设置“ no _ rw _ check”值指示 Quartus Prime 编译器不需要保留 HDL 源代码在写入过程中的读取行为。

您可以在单个属性中同时指定块类型和“ no _ rw _ check”，方法是用逗号分隔值，例如“ no _ rw _ check，M144K”，或者只指定块类型或“ no _ rw _ check”。

你也可以在推断出的 RAM 的变量声明之后的注释中嵌入 ramstyle synthesis 属性，如下面的代码所示:

reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M144K" */;