1.procedural assignments are used for updating reg ,integer , time ,real,realtime and memory data types.

2.difference between procedural assignments and continuous assignments

   (1)continuous assignments drive nets and are evaluated and updated whenever an input operand changes value.

(2)procedural assignments update the value of variables under the control of the procedural flow constructs that surround them.

variables <= / = expression

variables : 1.reg , integer, real,realtime,time

2.bit-select of a reg , integer,time

3.part-select of a reg ,integer, time

4.memory word

5,concatenation or nested concatenation of any of the above

note:如果左右边数据位宽不一致，需要进行零扩展、符号扩展。

3.procedural assignments

----blocking procedural assignment statements

----nonblocking procdedural assignment statements

blocking and nonblocking procedural assignment statements specify different procedural flows in sequential blocks

4.blocking assignment vs nonblocking assignments

5.assign vs deassign

6.force vs release

verilog behavioral modeling --procedural assignments的更多相关文章

  1. verilog behaviral modeling -- procedural timing contronls

    1.delay control : an expression specifies the time duration between initially encountering the state ...

  2. verilog behavioral modeling ---Block statements

    block statements : 1. sequential block  : begin-end block 2.parallel block       :  fork - join bloc ...

  3. verilog behavioral modeling --loop statement

    1.forever 2.repeat 3.while 4.for The for statement accomplishes the same results as the following ps ...

  4. verilog behavioral modeling--overview

    1.verilog behavioral models contain procedural statements that control the simulation and manipulate ...

  5. verilog behavioral modeling--procedural continous assignment(不用)

    assign / deassgin force /release the procedural continuous assignments(using keywords assign and for ...

  6. verilog behavioral modeling--blocking and nonblocking

                                                                                                 BLOCKIN ...

  7. verilog behavioral modeling--branch statement

    conditional statement case statement 1. conditional statement     if(expression)         statement_o ...

  8. verilog behavioral modeling--sequential and parallel statements

    1.Sequential statement groups the begin-end keywords: .group several statements togethor .cause the ...

  9. verilog FAQ(zz)

    1. What is the race condition in verilog? Ans :The situation when two expressions are allowed to exe ...

随机推荐

  1. 解决https接口 以及谷歌错误

    <meta http-equiv="Content-Security-Policy" content="block-all-mixed-content"& ...

  2. SpringBoot | Data Access

    https://docs.spring.io/spring-boot/docs/current/reference/html/howto-data-access.html 配置数据源启动器.

  3. django_auth模块

    auth是django提供的标准权限管控系统,可以提供用户的身份认证.用户组和权限管理. auth可以和admin配合使用,可以快速建立网站的管理系统. USER user用于维护系统的用户信息,在数 ...

  4. bzoj1492 [NOI2007]货币兑换Cash【cdq分治】

    传送门:http://www.lydsy.com/JudgeOnline/problem.php?id=1492 推荐博客:http://www.cnblogs.com/zig-zag/archive ...

  5. CVE-2012-0002（MS12-020）3389远程溢出漏洞

    1:攻击机:Kali和windows皆可 2:目标机:windows XP系统(开启3389) Kali测试: search m12-020 搜索ms12-020 use auxiliary/dos/ ...

  6. keil_rtx特点

    Keil RTX是一个专为ARM及Cortex M系列处理器开发的无版税的确定的实时操作系统.它允许工程师建立多任务同步并行的程序软件,同时也能帮助使程序代码更加结构化和便于维护.   产品亮点 所有 ...

  7. R 语言中 data table 的相关，内存高效的 增量式 data frame

    面对的是这样一个问题,不断读入一行一行数据,append到data frame上,如果用dataframe,  rbind() ,可以发现数据大的时候效率明显变低. 原因是 每次bind 都是一次重新 ...

  8. Oracle如何创建表空间

    create user frame identified by tiger; grant create session to frame; grant create table to frame; g ...

  9. P1791 线段覆盖

    题目描述 已知数轴上0<N<10000条线段.每条线段按照端点Ai和Bi(Ai<>Bi,i=1..N)定义.端点坐标在(-999,999)内,坐标为整数.有些线段可能相交.编程 ...

  10. PeopleSoft FSCM Production Support 案例分析之一重大紧急事故发生时的应对策略

    案例背景: 今天一大早用户打电话来讲昨天上传的银行的forex payment return file好像没有被处理到,我一听就觉得纳闷,因为昨天晚上operator也没有给我打电话啊(如果有job ...