Verilog整理

1.两种实例化

2.运算符//逻辑运算+按位运算//拼接运算符

3.reg默认为1位

4.{16{1}}与{16{1'b1}}不同

5.[1023:0] in

　　ha[3:0]=(in>>(4*sel))

6.三位全加器

  module add( 

                 input a, b, cin,

                 output cout, sum 

         );
  assign cout=a&b|a&cin|b&cin,sum=a^b^cin;
  endmodule
  module top_module( 

                 input [:] a, b,

                 input cin,

                 output [:] cout,

                 output [:] sum );
     add a0(a[],b[],cin,cout[],sum[]);
     add a1(a[],b[],cout[],cout[],sum[]);
     add a2(a[],b[],cout[],cout[],sum[]);
 endmodule

7. 区别reg a[7:0]与reg [7:0]a.

8.区分output reg out=0与output reg out

9.always不能嵌套

10.检测上升沿下降沿的小算法

module top_module (
    input clk,
    input [:] in,
    output [:] anyedge
);
reg [:] e,pd;
assign anyedge=pd;
integer i;
always  @(posedge clk)begin
    for(i=;i<;i=i+)
        e[i]<=in[i];
end
always @(posedge clk)begin
    for(i=;i<;i=i+)
        if(!e[i]&&in[i])
            pd[i]<=;
        else pd[i]=;
end
always @(posedge clk)begin
    for(i=;i<;i=i+)
        if(e[i]&&!in[i])
            pd[i]<=;
        else pd[i]=;
end
endmodule