modesim测试语句

:    fork  Reg1 = 'd2; Reg2 <= Reg1; i <= i + 1'b1; join
:    fork  Reg2 <= Reg1;Reg1 = 'd2; i <= i + 1'b1; join
:    begin  Reg1 = 'd2; Reg2 <= Reg1; i <= i + 1'b1; end
:    begin  Reg2 <= Reg1;Reg1 = 'd2; i <= i + 1'b1; end

均是按顺序执行？

1. always @ ( 铭感区域 ) Reg1 <= ~Reg1;
2. always @ ( * ) Reg1 = ~Reg1;
3. always Reg1 <= ~Reg1;
4. forever Reg1<= ~Reg1;

3.4为验证语法，综合无法实现

过程控制：

`timescale  ps/  ps
module exp09_simulation();

    /*********************/ // environment signal
    reg CLK, RSTn;

    initial
        begin
        CLK = ; RSTn = ; #; RSTn = ;
         end
          always # CLK = ~CLK;
      /********************/

    initial $monitor($time,,,"clk=%b i=%d j=%d",CLK, i, j);

    reg [:]i;
    reg [:]j;
    reg [:]Reg1;

    always @ ( posedge CLK or negedge RSTn )
        if( !RSTn )
            begin
                i <= 'd0;
                Reg1 <= 'd0;
            end
        else
            case( i )

                :
                begin Reg1 <= 'd1; i <= i + 1'b1; end

                :
                begin Reg1 <= 'd2; i <= i + 1'b1; end

                :
                if( j == ) i <= i + 'b1;

                :
                begin Reg1 <= 'd3; i <= i + 1'b1; end

            endcase

    /********************/    

    reg [:]Reg2;

    always @ ( posedge CLK or negedge RSTn )
        if( !RSTn )
            begin
                j <= 'd0;
                Reg2 <= 'd0;
            end
        else
            case( j )

                :
                if( i ==  ) j <= j + 'b1;

                :
                begin Reg2 <= 'd1; j <= j + 1'b1; end

                :
                j <= j;

                :
                begin Reg2 <= 'd2; j <= j + 1'b1; end    

            endcase

    /********************/    

endmodule