用Verilog实现IIC通讯
注意，此代码是错误代码，并不能实现想要的结果。
之所以留着，因为里面的enable 是独立开来的思想值得借鉴。就是控制单元和运算单元分开（我也是借鉴别人的实现思想）。具体用verilogHDL实现IIC通讯在http://www.cnblogs.com/sepeng/p/3258705.html 里会做到。
//date :2013/7/7
//designer :pengxiaoen
//synthesizer:QuartusII 12.1
//function : IIC实现HMC5883的通讯 50M /(400k × 4)= 32 `define WriteAddress 'h3c
`define ReadAddress 'h3d `define RegAAddress 'h00 //配置寄存器A
`define RegBAddress 'h01 //配置寄存器B
`define ModelAddress 'h02 //模式寄存器
`define X_MSBAddress 'h03 //X MSB寄存器
`define X_LSBAddress 'h04
`define Z_MSBAddress 'h05
`define Z_LSBAddress 'h06
`define Y_MSBAddress 'h07
`define Y_LSBAddress 'h08
`define STATEAddress 'h09 //状态寄存器
`define IdentifyAAddress 'h10 //识别寄存器A
`define IdentifyBAddress 'h10
`define IdentifyCAddress 'h10 `define INITIAL
`define MEASURE `define START
`define Re
`define Se
`define STOP //`default_nettype none module HMC5883_IIC (
clock,reset,
sda,scl,
out_seg, sel_seg
); input clock,reset;
inout sda,scl;
output reg [:]out_seg; output reg [:]sel_seg; reg [:] SEND_buffer;
reg [:] Re_buffer ;
reg sda_reg;
reg scl_reg;
reg sda_enable;
reg scl_enable; reg IC_state;
reg [:]state; //当前状态寄存器
reg state_finish_flag ; // reg [:] clk_counter;
reg [:] step_counter;
reg [:] clk_temp ; //-------------------------时钟控制模块-------------------------------start------------------
always @ (posedge clock or negedge reset)
if (!reset)
begin
clk_temp <= 'd0;
clk_counter <= 'd0;
end
else if (clk_temp[])
begin
clk_temp <= 'd0;
if (state_finish_flag) clk_counter <= 'd0;
else if (clk_counter == 'b111_111) //这里是一个保护机制，可以设置一个flag
begin
clk_counter <= 'b111_111;
end
else clk_counter <= clk_counter + ;
end
else clk_temp <= clk_temp + ;
//-------------------------时钟控制模块-----------------------------------end------------------ //-----------------状态机控制模块------------------------------------------start-------------------
always @ (posedge clock or negedge reset)
if(!reset)
IC_state <= `INITIAL;
else IC_state <= `MEASURE; always @ (posedge clock or negedge reset)
if (!reset)
begin
step_counter <= 'd0;
SEND_buffer <= 'd0;
end
else if(IC_state == `INITIAL)
case (step_counter)
: begin state <= `START; step_counter <= step_counter + ;end
: begin SEND_buffer <= 'h3c;state <= `Se; step_counter <= step_counter + 1; end
: begin SEND_buffer <= 'h02;state <= `Se; step_counter <= step_counter + 1; end
: begin SEND_buffer <= 'h00;state <= `Se; step_counter <= step_counter + 1; end
: begin SEND_buffer <= 'h00;state <= `Se; step_counter <= step_counter + 1; end
default step_counter <= 'd0;
endcase
else if (IC_state == `MEASURE)
case (step_counter)
: begin state <= `START; step_counter <= step_counter + ;end
: begin SEND_buffer <= 'h3c;state <= `Se; step_counter <= step_counter + 1; end
: begin SEND_buffer <= 'h03;state <= `Se; step_counter <= step_counter + 1; end
: begin state <= `START; step_counter <= step_counter + ;end
: begin SEND_buffer <= 'h3d;state <= `Se; step_counter <= step_counter + 1; end : begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end
: begin state <= `Re; step_counter <= step_counter + ; end : begin state <= `STOP; step_counter <= 'd0; end
default step_counter <= 'd0;
endcase //-----------------状态机控制模块-------------------------------------------end--------------------- //------------------------------------------使能控制模块--------------------------start---------------
always @ (posedge clk_counter or negedge reset)
if (!reset)
begin
sda_enable <= 'd0;
scl_enable <= 'd0;
end
else case (state)
`START : begin
if(clk_counter >= 'd4)
begin
sda_enable <= 'd0;
scl_enable <= 'd0;
end
else
begin
sda_enable <= 'd1;
scl_enable <= 'd1;
end
end `STOP : begin
if(clk_counter >= 'd4)
begin
sda_enable <= 'd0;
scl_enable <= 'd0;
end
else
begin
sda_enable <= 'd1;
scl_enable <= 'd1;
end
end `Se : begin
if(clk_counter >= 'd36) //send 完成之后释放掉使能
begin
sda_enable <= 'd0;
scl_enable <= 'd0;
end
else
begin
sda_enable <= 'd1;
scl_enable <= 'd1;
end
end `Re : begin
if(clk_counter >= 'd32) //receive 完成之后释放掉使能
begin
sda_enable <= 'd0;
scl_enable <= 'd0;
end
else
begin
sda_enable <= 'd1;
scl_enable <= 'd1;
end
end
endcase
//------------------------------------------使能控制模块--------------------------end--------------- //------------------------------------------------外部数据线 控制模块-----------------start---------------
always @ (posedge clk_counter or negedge reset)
if(!reset)
begin
sda_reg <= 'd0;
scl_reg <= 'd0;
state_finish_flag <= 'd0;
Re_buffer <= 'd0;
end
else case (state)
`START : begin
case (clk_counter)
: begin sda_reg <= 'd1; scl_reg <= 1'd0; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd1; scl_reg <= 1'd0; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd1; scl_reg <= 1'd1; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd0; scl_reg <= 1'd1; state_finish_flag <= 'd0; end
default begin sda_reg <= 'dz; scl_reg <= 1'dz; state_finish_flag <= 'd1; end
endcase
end `STOP : begin
case (clk_counter)
: begin sda_reg <= 'd0; scl_reg <= 1'd0; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd0; scl_reg <= 1'd0; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd0; scl_reg <= 1'd1; state_finish_flag <= 'd0; end
: begin sda_reg <= 'd1; scl_reg <= 1'd1; state_finish_flag <= 'd0; end
default begin sda_reg <= 'dz; scl_reg <= 1'dz; state_finish_flag <= 'd1; end
endcase
end `Se : begin
case (clk_counter)
: begin sda_reg <= 'd0; scl_reg <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin sda_reg <= SEND_buffer[]; scl_reg <= 'd1; state_finish_flag <= 1'd0; end : begin /*state_finish_flag <= sda;*/ scl_reg <= 'd0; /*state_finish_flag <= 1'd0; */ end
: begin /*state_finish_flag <= sda;*/ scl_reg <= 'd0; /*state_finish_flag <= 1'd0; */ end
: begin /*state_finish_flag <= sda;*/ scl_reg <= 'd1; /*state_finish_flag <= 1'd0; */ end
: begin state_finish_flag <= sda; scl_reg <= 'd1; /*state_finish_flag <= 1'd0; */ end default begin scl_reg <= 'dz; state_finish_flag <= sda; end //等待响应
endcase
end `Re : begin
case (clk_counter)
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end : begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd0; state_finish_flag <= 1'd0; end
: begin scl_reg <= 'd1; state_finish_flag <= 1'd0; end
: begin Re_buffer[] <= sda; scl_reg <= 'd1; state_finish_flag <= 1'd0; end // 32:begin sda_reg <= 1'd0; scl_reg <= 1'd0; state_finish_flag <= 1'd0; end //NA
// 33:begin sda_reg <= 1'd0; scl_reg <= 1'd0; state_finish_flag <= 1'd0; end
// 34:begin sda_reg <= 1'd0; scl_reg <= 1'd1; state_finish_flag <= 1'd0; end
// 35:begin sda_reg <= 1'd0; scl_reg <= 1'd1; state_finish_flag <= 1'd0; end default begin sda_reg <= 'dz; scl_reg <= 1'dz; state_finish_flag <= 'd1; end
endcase
end
endcase
//------------------------------------------------外部数据线 控制模块-----------------end--------------- assign sda = sda_enable ? sda_reg : 'dz ;
assign scl = scl_enable ? scl_reg : 'dz ; always @ (posedge clk_counter or negedge reset)
if (!reset)
begin sel_seg <= 'b111110;
end
else if(state_finish_flag)
begin
sel_seg <= {sel_seg[:],sel_seg[]};
end always @(posedge clock or negedge reset)
if (!reset) out_seg <= 'd0;
else
begin
case (Re_buffer)
'b0000 : out_seg<=8'b1100_0000;//0000_0011
'b0001 : out_seg<=8'b1111_1001;//1001_1111
'b0010 : out_seg<=8'b1010_0100;//0010_0101
'b0011 : out_seg<=8'b1011_0000;//0000_1101
'b0100 : out_seg<=8'b1001_1001;//1001_1001
'b0101 : out_seg<=8'b1001_0010;//0100_1001
'b0110 : out_seg<=8'b1000_0010;//0100_0001
'b0111 : out_seg<=8'b1111_1000;//0001_1111
'b1000 : out_seg<=8'b1000_0000;//0000_0001
'b1001 : out_seg<=8'b1001_1000;//0001_1001
'b1010 : out_seg<=8'b1000_1000;//0001_0001
'b1011 : out_seg<=8'b1000_0011;//1100_0001
'b1100 : out_seg<=8'b1100_0110;//0110_0011
'b1101 : out_seg<=8'b1010_0001;//1000_0101
'b1110 : out_seg<=8'b1000_0110;//0110_0001
'b1111 : out_seg<=8'b1000_1110;//0111_0001
endcase
end endmodule
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