s3c2440 移值u-boot-2016.03 第2篇 支持Nand flash启动
1, 要求：在4K 的代码以内，完成 NOR NAND 类型判断，初始化 NAND 复制自身到 SDRAM ，重定向。
2, 在 /arch/arm/cpu/arm920t/ 文件夹里 添加一个 inic.c 的文件，要在这个文件里面做上面说的事情。
修改 /arch/arm/cpu/arm920t/Makefile 加入 inic.c 的 编译。
extra-y = start.o
obj-y += init.o
obj-y += cpu.o
init.c 最后有补丁文件
3, 在 start.S 中初始化 SP 后调用 init.c 中的 初始化 NAND FLASH 和 复制 u-boot 到 SDRAM 清BSS 等
ldr sp, =4096 #在 NOR 启动时定在这里是不能写的，sp 中通常是保存 入栈 出栈 ， 局部变量等，因为函数中并没有用到，设不设这里都可以。
bl init_sdram
ldr sp, =0x34000000
bl nand_init_ll
/**
* 从 0 地址开始复制 到 SDRAM 中
* 在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE
* u-boot 的加载地址
*/
mov r0,#0
ldr r1,=CONFIG_SYS_TEXT_BASE
ldr r2,=__bss_start
sub r2, r2, r1
bl copy_code_to_sdram
bl clear_bss #清不清都可以，因为重定向那里还要在清一次，为了以后去掉重定向这里也清。
#从片内 4K 跳到 SDRAM 中 bl 不行，要用 ldr pc
ldr pc,=_main
4, 启用流程
/arch/arm/cpu/arm920t/start.S
/arch/arm/lib/crt0.S
u-boot 第一阶段
/common/Board_f.c 中的 board_init_f() 函数
最后调用
jump_to_copy()
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
调用/arch/arm/librelocate.S relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
执行完毕后返回
crt0.S
bl board_init_f
下面直接执行第2阶段，也是因为执行了重定位，bl 跳不了
ldr pc, =board_init_r
5, 如何兼容 NOR FLASH NAND FLASH 启用？
不改动 原来的 重定位代码比较简单。
兼容 NOR FLASH NAND FLASH 的方法是，如果不想修改重定位的代码，就是先把 u-boot 复制到
SDRAM 的一个低地址，然后，它会从 这里在复制到 SDRAM 的高地址去。
NAND FLASH 启用要做的就是，在 4K 自动复制的代码里面，实现把u-boot 复制到 SDRAM 的低地址
6, 确定一个可用的链接地址
crt0.S
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
这里先把 sp 定在了最低端，因此不能使用 0x30000000
又因为u-boot 最终会被放到高地址也不能用 0x34000000
因为内存很大，放在10M 的位置吧。
在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE 0x30a00000
补丁文件：
diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/init.c u-boot-2016.03-ok/arch/arm/cpu/arm920t/init.c
--- u-boot-2016.03/arch/arm/cpu/arm920t/init.c -- ::00.000000000 +
+++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/init.c -- ::31.635438931 +
@@ -, +, @@
+/* NAND FLASH控制器 */
+#define NFCONF (*((volatile unsigned long *)0x4E000000))
+#define NFCONT (*((volatile unsigned long *)0x4E000004))
+#define NFCMMD (*((volatile unsigned char *)0x4E000008))
+#define NFADDR (*((volatile unsigned char *)0x4E00000C))
+#define NFDATA (*((volatile unsigned char *)0x4E000010))
+#define NFSTAT (*((volatile unsigned char *)0x4E000020))
+
+/* CLK */
+#define CLKDIVN (*(volatile unsigned long *)0x4C000014)
+#define MPLLCON (*(volatile unsigned long *)0x4C000004)
+
+/* SDRAM */
+#define BWSCON (*(volatile unsigned long *)0x48000000)
+#define BANKCON6 (*(volatile unsigned long *)0x4800001c)
+#define REFRESH (*(volatile unsigned long *)0x48000024)
+#define BANKSIZE (*(volatile unsigned long *)0x48000028)
+#define MRSRB6 (*(volatile unsigned long *)0x4800002c)
+
+void init_clock(void)
+{
+ //Mpll = 400M
+ MPLLCON = (0x5c<<) | (<<) | ;
+ //FCLK 400M HCLK 100M PCLK 50M
+ CLKDIVN = << | <<;
+ __asm__(
+ "mrc p15,0,r0,c1,c0,0\n"
+ "orr r0,r0,#0xc0000000\n"
+ "mcr p15,0,r0,c1,c0,0\n"
+ );
+}
+
+void init_sdram(void)
+{
+ BWSCON = <<;
+ BANKCON6 = << | << | ;
+ REFRESH = (<<) + ;
+ BANKSIZE = << | << | ;
+ MRSRB6 = 0x30;
+}
+
+void clear_bss(void)
+{
+ extern int __bss_start, __bss_end;
+ int *p = &__bss_start;
+
+ for (; p < &__bss_end; p++)
+ {
+ *p = ;
+ }
+}
+
+static void nand_latency(void)
+{
+ int i=;
+ while(i--);
+}
+
+static void nand_is_ready(void)
+{
+ //bit 0 : 1 不忙了
+ while(! (NFSTAT & ));
+}
+
+static void nand_write_addr(unsigned int addr)
+{
+ int col, page;
+ col = addr % ;
+ page = addr / ;
+
+ NFADDR = col & 0xff; /* Column Address A0~A7 */
+ nand_latency();
+ NFADDR = (col >> ) & 0x0f; /* Column Address A8~A11 */
+ nand_latency();
+ NFADDR = page & 0xff; /* Row Address A12~A19 */
+ nand_latency();
+ NFADDR = (page >> ) & 0xff; /* Row Address A20~A27 */
+ nand_latency();
+ NFADDR = (page >> ) & 0x03; /* Row Address A28~A29 */
+ nand_latency();
+}
+
+static unsigned char nand_read_char(void)
+{
+ //只保留8个bit
+ return NFDATA & 0xff;
+}
+
+static void nand_cmd(unsigned char cmd)
+{
+ NFCMMD = cmd;
+ nand_latency();
+}
+
+static void nand_select_chip(void)
+{
+ //1bit : 0 选中
+ NFCONT &= ~(<<);
+}
+
+static void nand_deselect_chip(void)
+{
+ //1bit : 1 选中
+ NFCONT |= (<<);
+}
+
+static void nand_reset(void)
+{
+ nand_select_chip();
+ nand_cmd(0xff);
+ nand_deselect_chip();
+}
+
+void nand_init_ll(void)
+{
+ //TACLS 3.3v 时 12ns
+ #define TACLS 0
+ //12ns
+ #define TWRPH0 1
+ //5ns
+ #define TWRPH1 0
+ NFCONF = TACLS<< | TWRPH0<< | TWRPH1<<;
+ /* 4 ECC
+ * 1 CE 先不选中，用的时候在选中
+ * 0 启动 flash controller
+ */
+ NFCONT = << | << | ;
+ nand_reset();
+}
+
+static void nand_read(unsigned int addr, unsigned char *buf, int len)
+{
+ //选中
+ nand_select_chip();
+ //j 地址可能不是从0对齐开始读的
+ unsigned int i = addr,j = addr % ;
+ for(; i<(addr + len);)
+ {
+ //读命令
+ nand_cmd(0x00);
+ nand_is_ready();
+
+ //发送地址
+ nand_write_addr(i);
+ nand_is_ready();
+
+ //在次发出读命令
+ nand_cmd(0x30);
+ nand_is_ready();
+ //读2K
+ for(; j<; j++)
+ {
+ *buf = nand_read_char();
+ buf++;
+ i++;
+ }
+ j=;
+ nand_latency();
+ }
+ //取消选中
+ nand_deselect_chip();
+}
+
+static int boot_is_nor()
+{
+ //利用 NOR 不能写的特点判断
+ volatile unsigned int *p = (volatile unsigned int *);
+ unsigned int val;
+ val = *p;
+ *p = 0x12345678;
+ if(0x12345678 == *p)
+ {
+ *p = val;
+ return ;
+ }
+ return ;
+}
+
+//片内4K 的程序要复制到链接SDRAM中去
+void copy_code_to_sdram(unsigned char *src,unsigned char *dst,int len)
+{
+ int i = ;
+ if(boot_is_nor())
+ {
+ while(i < len)
+ {
+ dst[i] = src[i];
+ i++;
+ }
+ }
+ else
+ {
+ nand_read((int)src, dst, len);
+ }
+}
+
diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/Makefile u-boot-2016.03-ok/arch/arm/cpu/arm920t/Makefile
--- u-boot-2016.03/arch/arm/cpu/arm920t/Makefile -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/Makefile -- ::31.767626866 +
@@ -, +, @@
extra-y = start.o obj-y += cpu.o
+obj-y += init.o
obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(CONFIG_EP93XX) += ep93xx/
diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/start.S u-boot-2016.03-ok/arch/arm/cpu/arm920t/start.S
--- u-boot-2016.03/arch/arm/cpu/arm920t/start.S -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/start.S -- ::31.782641369 +
@@ -, +, @@ /* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #
- str r1, [r0]
+ //ldr r0, =CLKDIVN
+ //mov r1, #3
+ //str r1, [r0]
+
+ /* 设置分频参数 */
+ ldr r0, =CLKDIVN
+ mov r1, #0x05; /* FCLK:HCLK:PCLK=1:4:8 */
+ str r1, [r0]
+
+ /* 如果HDIVN非0，CPU的总线模式应该从“fast bus mode”变为“asynchronous bus mode” */
+ mrc p15, , r1, c1, c0, /* 读出控制寄存器 */
+ orr r1, r1, #0xc0000000 /* 设置为“asynchronous bus mode” */
+ mcr p15, , r1, c1, c0, /* 写入控制寄存器 */
+
+ /* 配置时钟 */
+ #define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01))
+ ldr r0, =0x4c000004
+ ldr r1, =S3C2440_MPLL_400MHZ
+ str r1, [r0]
+
#endif /* CONFIG_S3C24X0 */ + /**
+ * 调用 init.c 中的初始化
+ * 因为已经初始化好内存 所以 sp 在 顶部
+ * 在 NOR 时不能用片内 4K
+ */
+ ldr sp, =
+ bl init_sdram
+ ldr sp, =0x34000000
+ bl nand_init_ll
+ /**
+ * 从 0 地址开始复制 到 SDRAM 中
+ * 在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE
+ * u-boot 的加载地址
+ */
+ mov r0,#
+ ldr r1, =CONFIG_SYS_TEXT_BASE
+ ldr r2, =__bss_start
+ sub r2, r2, r1
+ bl copy_code_to_sdram
+ bl clear_bss
+ ldr pc, =_main
+
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
@@ -95,8 +134,6 @@
bl cpu_init_crit
#endif - bl _main
-
/*------------------------------------------------------------------------------*/ .globl c_runtime_cpu_setup
diff -urN u-boot-2016.03/arch/arm/cpu/u-boot.lds u-boot-2016.03-ok/arch/arm/cpu/u-boot.lds
--- u-boot-2016.03/arch/arm/cpu/u-boot.lds -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/cpu/u-boot.lds -- ::12.338040880 +
@@ -, +, @@
*/
/DISCARD/ : { *(.rel._secure*) }
#endif
- . = 0x00000000;
+ . = ; . = ALIGN();
.text :
diff -urN u-boot-2016.03/arch/arm/Kconfig u-boot-2016.03-ok/arch/arm/Kconfig
--- u-boot-2016.03/arch/arm/Kconfig -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/Kconfig -- ::52.118143749 +
@@ -, +, @@
config TARGET_SMDK2410
bool "Support smdk2410"
select CPU_ARM920T
+
+config TARGET_SMDK2440
+ bool "Support smdk2440"
+ select CPU_ARM920T config TARGET_ASPENITE
bool "Support aspenite"
@@ -, +, @@
source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/samsung/smdk2410/Kconfig"
+source "board/samsung/smdk2440/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
diff -urN u-boot-2016.03/arch/arm/lib/crt0.S u-boot-2016.03-ok/arch/arm/lib/crt0.S
--- u-boot-2016.03/arch/arm/lib/crt0.S -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/lib/crt0.S -- ::44.287690421 +
@@ -, +, @@
* relocate_code(addr_moni). Trick here is that we'll return
* 'here' but relocated.
*/
-
ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */
#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */
mov r3, sp
@@ -, +, @@ bl c_runtime_cpu_setup /* we still call old routine here */
#endif
+
+
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
-# ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
cmp r0, #
movne sp, r0
movne r9, r0
-# endif
+#endif
+
ldr r0, =__bss_start /* this is auto-relocated! */ #ifdef CONFIG_USE_ARCH_MEMSET
@@ -, +, @@
#endif ENDPROC(_main)
+
diff -urN u-boot-2016.03/arch/arm/lib/relocate.S u-boot-2016.03-ok/arch/arm/lib/relocate.S
--- u-boot-2016.03/arch/arm/lib/relocate.S -- ::21.000000000 +
+++ u-boot-2016.03-ok/arch/arm/lib/relocate.S -- ::48.481661370 +
@@ -, +, @@ ENTRY(relocate_vectors) +
#ifdef CONFIG_CPU_V7M
/*
* On ARMv7-M we only have to write the new vector address
diff -urN u-boot-2016.03/board/samsung/smdk2440/Kconfig u-boot-2016.03-ok/board/samsung/smdk2440/Kconfig
--- u-boot-2016.03/board/samsung/smdk2440/Kconfig 1970-01-01 07:00:00.000000000 +0700
+++ u-boot-2016.03-ok/board/samsung/smdk2440/Kconfig 2016-05-16 21:51:04.391251360 +0800
@@ -0,0 +1,15 @@
+if TARGET_SMDK2440
+
+config SYS_BOARD
+ default "smdk2440"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_SOC
+ default "s3c24x0"
+
+config SYS_CONFIG_NAME
+ default "smdk2440"
+
+endif
diff -urN u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S u-boot-2016.03-ok/board/samsung/smdk2440/lowlevel_init.S
--- u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S 1970-01-01 07:00:00.000000000 +0700
+++ u-boot-2016.03-ok/board/samsung/smdk2440/lowlevel_init.S 2016-05-16 21:51:04.246938015 +0800
@@ -0,0 +1,147 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <config.h>
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, =CONFIG_SYS_TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #*
+:
+ ldr r3, [r0], #
+ str r3, [r1], #
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .long 0x22011110 //BWSCON
+ .long 0x00000700 //BANKCON0
+ .long 0x00000700 //BANKCON1
+ .long 0x00000700 //BANKCON2
+ .long 0x00000700 //BANKCON3
+ .long 0x00000740 //BANKCON4
+ .long 0x00000700 //BANKCON5
+ .long 0x00018005 //BANKCON6
+ .long 0x00018005 //BANKCON7
+ .long 0x008C04F4 // REFRESH
+ .long 0x000000B1 //BANKSIZE
+ .long 0x00000030 //MRSRB6
+ .long 0x00000030 //MRSRB7
+
diff -urN u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS u-boot-2016.03-ok/board/samsung/smdk2440/MAINTAINERS
--- u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS -- ::00.000000000 +
+++ u-boot-2016.03-ok/board/samsung/smdk2440/MAINTAINERS -- ::04.335323843 +
@@ -, +, @@
+SMDK2440 BOARD
+M: David M眉ller <d.mueller@elsoft.ch>
+S: Maintained
+F: board/samsung/smdk2440/
+F: include/configs/smdk2440.h
+F: configs/smdk2440_defconfig
diff -urN u-boot-2016.03/board/samsung/smdk2440/Makefile u-boot-2016.03-ok/board/samsung/smdk2440/Makefile
--- u-boot-2016.03/board/samsung/smdk2440/Makefile -- ::00.000000000 +
+++ u-boot-2016.03-ok/board/samsung/smdk2440/Makefile -- ::04.451323638 +
@@ -, +, @@
+#
+# (C) Copyright -
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := smdk2440.o
+obj-y += lowlevel_init.o
diff -urN u-boot-2016.03/board/samsung/smdk2440/smdk2440.c u-boot-2016.03-ok/board/samsung/smdk2440/smdk2440.c
--- u-boot-2016.03/board/samsung/smdk2440/smdk2440.c -- ::00.000000000 +
+++ u-boot-2016.03-ok/board/samsung/smdk2440/smdk2440.c -- ::04.267044306 +
@@ -, +, @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002, 2010
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */
+#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if (USB_CLOCK == 0)
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif (USB_CLOCK == 1)
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ writel(0xFFFFFF, &clk_power->locktime);
+
+ /* configure MPLL */
+ //writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);
+
+ /* some delay between MPLL and UPLL */
+ //pll_delay(4000);
+
+ /* configure UPLL */
+ writel((U_M_MDIV << ) + (U_M_PDIV << ) + U_M_SDIV,
+ &clk_power->upllcon);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay();
+
+ /* set up the I/O ports */
+ writel(0x007FFFFF, &gpio->gpacon);
+ writel(0x00044555, &gpio->gpbcon);
+ writel(0x000007FF, &gpio->gpbup);
+ writel(0xAAAAAAAA, &gpio->gpccon);
+ writel(0x0000FFFF, &gpio->gpcup);
+ writel(0xAAAAAAAA, &gpio->gpdcon);
+ writel(0x0000FFFF, &gpio->gpdup);
+ writel(0xAAAAAAAA, &gpio->gpecon);
+ writel(0x0000FFFF, &gpio->gpeup);
+ writel(0x000055AA, &gpio->gpfcon);
+ writel(0x000000FF, &gpio->gpfup);
+ writel(0xFF95FFBA, &gpio->gpgcon);
+ writel(0x0000FFFF, &gpio->gpgup);
+ writel(0x002AFAAA, &gpio->gphcon);
+ writel(0x000007FF, &gpio->gphup);
+
+ return ;
+}
+
+int board_init(void)
+{
+ /* arch number of SMDK2410-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return ;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return ;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = ;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(, CONFIG_CS8900_BASE);
+#endif
+ return rc;
+}
+#endif
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29LV800BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return ;
+}
diff -urN u-boot-2016.03/configs/smdk2440_defconfig u-boot-2016.03-ok/configs/smdk2440_defconfig
--- u-boot-2016.03/configs/smdk2440_defconfig -- ::00.000000000 +
+++ u-boot-2016.03-ok/configs/smdk2440_defconfig -- ::48.822806092 +
@@ -, +, @@
+CONFIG_ARM=y
+CONFIG_TARGET_SMDK2440=y
+CONFIG_SYS_PROMPT="SMDK2440 # "
+# CONFIG_CMD_SETEXPR is not set
diff -urN u-boot-2016.03/include/configs/smdk2410.h u-boot-2016.03-ok/include/configs/smdk2410.h
--- u-boot-2016.03/include/configs/smdk2410.h -- ::21.000000000 +
+++ u-boot-2016.03-ok/include/configs/smdk2410.h -- ::46.907513241 +
@@ -, +, @@
* (easy to change)
*/
#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
-#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_S3C2440
#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ -#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_SYS_TEXT_BASE 0x33f00000 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
@@ -, +, @@
/************************************************************
* USB support (currently only works with D-cache off)
************************************************************/
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_OHCI_S3C24XX
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
+/*#define CONFIG_USB_OHCI */
+/*#define CONFIG_USB_OHCI_S3C24XX */
+/*#define CONFIG_USB_KEYBOARD */
+/*#define CONFIG_USB_STORAGE */
+/*#define CONFIG_DOS_PARTITION */ /************************************************************
* RTC
************************************************************/
-#define CONFIG_RTC_S3C24X0
+/*#define CONFIG_RTC_S3C24X0*/ #define CONFIG_BAUDRATE 115200
@@ -, +, @@
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+/*#define CONFIG_BOOTP_BOOTFILESIZE*/
+/*#define CONFIG_BOOTP_BOOTPATH*/
+/*#define CONFIG_BOOTP_GATEWAY*/
+/*#define CONFIG_BOOTP_HOSTNAME*/ /*
* Command line configuration.
*/
-#define CONFIG_CMD_BSP
+/*#define CONFIG_CMD_BSP*/
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
+/*#define CONFIG_CMD_DATE*/
+/*#define CONFIG_CMD_DHCP*/
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_USB
+/*#define CONFIG_CMD_REGINFO*/
+/*#define CONFIG_CMD_USB*/ #define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
@@ -, +, @@
#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.0.110
-#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_IPADDR 192.168.1.88
+#define CONFIG_SERVERIP 192.168.1.1 #if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
@@ -, +, @@
* NAND configuration
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_S3C2410_NAND_HWECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x4E000000
+#define CONFIG_NAND_S3C2440
+#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
+#define CONFIG_S3C24XX_TACLS 1
+#define CONFIG_S3C24XX_TWRPH0 2
+#define CONFIG_S3C24XX_TWRPH1 1
#endif /*
* File system
*/
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
+/*#define CONFIG_CMD_FAT*/
+/*#define CONFIG_CMD_EXT2*/
+/*#define CONFIG_CMD_UBI*/
+/*#define CONFIG_CMD_UBIFS*/
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_YAFFS2
-#define CONFIG_RBTREE
+/*#define CONFIG_RBTREE*/ /* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
diff -urN u-boot-2016.03/include/configs/smdk2440.h u-boot-2016.03-ok/include/configs/smdk2440.h
--- u-boot-2016.03/include/configs/smdk2440.h -- ::00.000000000 +
+++ u-boot-2016.03-ok/include/configs/smdk2440.h -- ::51.777785587 +
@@ -, +, @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <garyj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Configuation settings for the SAMSUNG SMDK2440 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2440 /* specifically a SAMSUNG S3C2440 SoC */
+#define CONFIG_SMDK2440 /* on a SAMSUNG SMDK2440 Board */
+
+#define CONFIG_SYS_TEXT_BASE 0x30a00000/*0x33f00000*/
+
+
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* input clock of PLL (the SMDK2440 has 12MHz input clock) */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */
+
+
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+#define CONFIG_CMD_PING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+
+/* autoboot */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.123
+#define CONFIG_SERVERIP 192.168.1.100
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x30800000
+
+/* support additional compression methods */
+#define CONFIG_BZIP2
+#define CONFIG_LZO
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT (19)
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 0x10000
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Size of malloc() pool
+ * BZIP2 / LZO / LZMA need a lot of RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_S3C2440
+#define CONFIG_SYS_S3C2440_NAND_HWECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4E000000
+#endif
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
diff -urN u-boot-2016.03/Makefile u-boot-2016.03-ok/Makefile
--- u-boot-2016.03/Makefile -- ::21.000000000 +
+++ u-boot-2016.03-ok/Makefile -- ::00.046292963 +
@@ -, +, @@
SUBLEVEL =
EXTRAVERSION =
NAME =
-
+ARCH=arm
+CROSS_COMPILE=arm-linux-
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
# More info can be located in ./README
Binary files u-boot-2016.03/.swp and u-boot-2016.03-ok/.swp differ
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