VHDL之conversion function

VHDL Type Cast and Conversion Functions

　　**In ASIC design, do NEVER use integer or natural for signals, use conversion functions instead**

　　The picture below illustrates how to convert between the most common VHDL types.

For example:　　

 signal good_example1    :    std_logic_vector( downto );
 signal good_example2    :    std_logic_vector( downto );

 good_example1  <=  std_logic_vector(to_unsigned(, good_example1'length));
 good_example2  <=  std_logic_vector(to_signed(, good_example2'length)); 

numeric_std

1   --===========================================================================
2   -- Numeric array type definitions
3   --===========================================================================

   type UNSIGNED is array (NATURAL range <> ) of STD_LOGIC;
   type SIGNED is array (NATURAL range <> ) of STD_LOGIC;