TC358746AXBG/748XBG 桥接器说明

为什么需要这个mipi csi-2 bridge 芯片，由于我们用的sensor 芯片是美光的MT9m021,这颗芯片并不支持MIPI

下面是网上摘录的说明可能解释这个问题：

Because of
the high volume and cost optimized design of these image sensors, many embedded application designers are
interested in using these CSI2 image sensors. The challenge is that traditional ISPs (Image Signal Processors) do
not have a CSI2 interface. Many have a traditional CMOS bus for camera interfaces. ISPs with a parallel CMOS
interface bus must use an external bridge to convert from CSI2 to parallel CMOS

TC358746AXBG/748XBG 桥接器是功能是把将来自设备的MIPI数据(诸如相机)到应用处理器转换成并行数据输出。

有两个接口： CSI-2 TX/RX Interface 和 Parallel Port Interface

可以配置成两种模式：

一种是：

Camera sensor的数据 -> bridge -> application， source 是: CSI-2 RX, target 端是 parallel output

块图如下：

这种模式对应的初始话代码如下：（针对芯片TC358746AXBG/748XBG，不同的做细微修改，具体根据datasheet说明）

对照寄存器解释一下这个初始化代码：

0x0002, 0x0001  //reset 1

0x0002, 0x0000  // reset 0 , 拉高再拉低，复位然后回到工作状态

0x0016, 0x40A0  // PLL Control Register 0， 设置分频比，反正是时钟的配置，具体的意义不明白，但是必须要配置的。

0x0018, 0x0013  // PLL Control Register 0， PLL reset + PLL enable + Clock enable

0x0020, 0x0000 //  时钟设置 (ppi_clk = PLL_CLK DIV 8) + (MclkRef = PLL_CLK DIV 8) +（sys_clk = PLL_CLK DIV 8）

0x000c, 0x0201 //  MCLK 设置， Total MClk divider = (mclk_high + 1) + (mclk_low + 1) = （2*MclkRef Count +1 ）+ （2*MclkRef Count +1 ）

0x0006, 0x0062 // FiFo Control Register， 设置一个leve值，当前的是6+2, when reaches to this level,FiFo controller asserts FiFoRdy for Parallel portto 　　　　　　　　　　　　 // startoutput data

0x0008, 0x0020 // data format, 设置为RAW12

0x0060, 0x8009 //  MIPI PHY Time Delay： Delay = (9+1) x PPIRXCLK， TC TERM selection 需要设置成1，也就是这个15bit 为1，即8

0x0004, 0x0044 //  Parallel Port Enable + i2c地址每个字节传输完后递增

第二种模式是顺序是反过来的，把并行数据转换成mipi输出， souce 是: parallel input,  target端是: CSI-2 TX

块图如下：

这种模式对应的初始化代码如下：

具体寄存器的意思查询dataSheet,解释如下：

0x0004,0x0004.   //   Parallel Data Format mode0 + PCLK Inverted(??我也不懂)

0x0002,0x0001.   //　　reset 1

0x0002,0x0000.   //      reset 0

0x0016,0x505d.   //    设置输入和feedback的分频比

0x0018,0x0213.   //  50% of maximum loop bandwidth+ PLL Clock enable + Normal operation + PLL enable

0x0006,0x0030.   //  FiFo Level = 3

0x0008,0x0020.   // Peripheral Data Format RAW12

0x0022,0x0780.   // Word count: define total number of byte for each line

0x0140,0x00000000.   // Clock Lane DPHY Control Register ,Bypass lane enable from PPILayer enable

0x0144,0x00000000.   // Data Lane 0 DPHY Control Register,Bypass lane enable from PPILayer enable

0x0148,0x00000001.   //Data Lane 1 DPHY Control Register, Force lane disable

0x014c,0x00000001.   //Data Lane 2 DPHY Control Register, Force lane disable

0x0150,0x00000001.   //Data Lane 3 DPHY Control Register, Force lane disable

0x0210,0x00002C00.   //

Line Initialization Wait Counter
This counter is used for line initialization.
Set this register before setting [STARTCNTRL].START = 1.
MIPI specification requires that the slave device needs to observe LP-11 for
100 us and ignore the received data before the period at initialization time.
The count value depends on HFCLK and the value needs to be set to achieve
more than 100 us. The counter starts after the START bit of the STARTCNTRL
register is set.
The Master device needs to output LP-11 for 100 us in order for the slave
device to observe LP-11 for the period.
For example, in order to set 100 us when the period of HFCLK is 12 ns, the
counter value should be more than 8333.3 = 0x208D (100 us / 12 ns). Default is
0x208E.

0x0214,0x00000005.   //

SYSLPTX Timing Generation Counter
The counter generates a timing signal for the period of LPTX.
This counter is counted using the HSByteClk (the Main Bus clock), and the
value of (setting + 1) *HSByteClk Period becomes the period LPTX. Be sure to
set the counter to a value greater than 50 ns.

0x0218,0x00001E06.   //

TCLK_ZERO Counter
This counter is used for Clock Lane control in the Master mode.
In order to satisfy the timing parameter TCLK-PRE + TCLK-ZERO for Clock Lane, this
counter is used.
This counter is counted by HSBYTECLk.
Set this register in order to set the minimum time (TCLK-PRE + TCLK-ZERO) to a
value greater than 300 ns.
The actual value is ((1 to 2) + (TCLK_ZEROCNT + 1)) x HSByteClkCycle + (PHY output
delay).
The PHY output delay is about (0 to 1) x HSByteClkCycle in the ByteClk conversion
performed during RTL simulation, and is about (2 to 3) x MIPIBitClk cycle in the
BitClk conversion.

TCLK_PREPARE Counter
This counter is used for Clock Lane control in the Master mode.
In order to satisfy the timing parameter TCLK-PREPARE for Clock Lane, this counter
is used.
This counter is counted by HSBYTECLK.
Set TCLK-PREPARE period that is greater than 38 ns but less than 95 ns.
Calculating formula (TCLK_PREPARECNT + 1) x HSByteClkCycle

0x021C,0x00000004.   //

TCLK_TRAIL Counter
This counter is used for Clock Lane control in Master mode.
In order to satisfy the timing parameter about TCLK-TRAIL and TEOT for
Clock Lane, this counter is used.
This counter is counted by HSBYTECLK.
Set this register in order to set TCLK-TRAIL to a value greater than 60 ns and
TEOT to a value less than 105 ns + 12 x UI
The actual value is (TCLK_TRAILCNT + (1 to 2)) xHSByteClkCycle + (2+(1 to
2)) * HSBYTECLKCycle - (PHY output delay).
The PHY output delay is about (0 to 1) xHSByteClkCycle in the ByteClk
conversion performed during RTL simulation, and is about (2 to 3)
xMIPIBitClk cycle in the BitClk conversion.

0x0220,0x00000406.   //

THS_ZERO Counter
This counter is used for Data Lane control in Master mode.
In order to satisfy the timing parameter about THS-PREPARE + THS-ZERO for Data
Lane, this counter is used.
This counter is counted by HSBYTECLK.
Set this register to set the (THS-PREPARE + THS-ZERO) period, which should be
greater than (145 ns + 10 x UI) results.
The actual value is ((1 to 2) + 1 + (TCLK_ZEROCNT + 1) + (3 to 4)) x ByteClk cycle +
HSByteClk x (2+(1 to 2)) +(PHY delay).
The PHY output delay is about (1 to 2) x HSByteClkCycle in the ByteClk conversion
performed during RTL simulation, and is about (8+(5 to 6)) x MIPIBitClk cycle in
BitClk conversion.

THS_PREPARE Counter
This counter is used for Data Lane control in Master mode.
In order to satisfy the timing parameter about THS-PREPARE for Data Lane, this
counter is used.
This counter is counted by HSBYTECLK.
Set this register in order to set the THS-PREPARE period, which should be greater
than (40 ns + 4xUI) and less than (8 5 ns + 6xUI) results.
Calculating Formula: (THS_PREPARECNT + 1) x HSByteClkCycle

0x0224,0x00004988.   //

TWAKEUP Counter
This counter is used to exit ULPS state. Ultra-Low Power State is exited by
TWAKEUPCNT
[15:0]
means of a Mark-1 state with a length TWAKEUP followed by a Stop state.
This counter is counted by the unit of LPTXTIMECNT.

0x0228,0x0000000C.   //

TCLK_POST Counter
This counter is used for Clock Lane control in Master mode.
This counter is counted by the HSByteClk.
Set a value greater than (60 ns + 52 x UI) results.
The actual value is ((1 to 2) + (TCLK_POSTCNT + 1)) x HSByteClk cycle + (1) x
HSBYTECLK cycle.

0x022C,0x00000006.   //

THS_TRAIL Counter
This counter is used for Data Lane control in Master mode.
This counter is counted by HSBYTECLK.
Set a value greater 8 x UI or (60 ns + 4 x UI) and less than TEOT which is
105 ns + 12 x UI results.
The actual value is (1 + THS_TRAILCNT) xByteClk cycle + ((1 to 2) + 2)
xHSBYTECLK cycle - (PHY output delay).
The PHY output delay is about (1 to 2) xHSByteClkCycle in ByteClk
conversion performed during RTL simulation and is about (8+(5 to 6))
xMIPIBitClk cycle in BitClk conversion.

0x0234,0x00000003.   //

Voltage regulator enable for HSTX Data Lane 0.+ Voltage regulator enable for HSTX Clock Lane.

0x0238,0x00000001.   // Continuous clock mode. Maintains the Clock Lane output regardless of the Data Lane operation

0x0204,0x00000001.   //

START control bit of PPI-TX function.
By writing 1 to this bit, PPI starts function.
0: Stop function. (default). Writing 0 is invalid and the bit can be set to zero by
system reset only.
1: Start function.
The following registers are set to appropriate value before starting any
transmission by START bit in STARTCTRL register. Once START bit is set to high,
the change of the register bits does not affect to function. In order to change
the values, initialization by RESET_N is necessary.

0x0518,0x00000001.   // CSI START

0x0500,0xA30080A1.   //The Lane indicated by LANE_ENA transitions to the LP stop state + Enable lane1,lane3

0x0004,0x0044.   //  Parallel Port Enable + I2C address index increments on every data byte transfer

S1:

TC358746AXBG/TC358748XBG has option
to generate XShutdown/CXRST/MCLK signals for camera device through GPIO[2:0] signals

S2:

TC358746AXBG/TC358748XBG supports 8-bit data bus (PD[7:0])or 24-bit data bus (PD[23:0]). 从原理图上可以看到有24个pin口，可以根据需要格式选择使用哪些pin口，最大支持RGB888，也就是24个pin口全都接上使用。

S3: support format

RAW8/10/12/14,

RGB888/666/565,

YUV422 8-bit on 8/16-bit bus and YUV422 10-bit

S4：

The Parallel Input controller received the video data from external. It then packed these into
32-bit data format then transfers the packed data into the Line buffer. The 32-bit data format is
showed in Table 4-3（这个是指原理图中的表4-3）
Parallel Input controller is operated with PCLK only. All asynchronous logic is handled inside
Video buffer Controller

S5:

PPI : PHY-Protocol Interface 物理协议接口层

S6:  Datasheet 关于寄存器0x0500有两种解释，不知道是怎么回事？

一种是：CSI Configuration Register (CSI_CONFW: 0x0500)

另一种是: CSI LP Command (CSI_LPCMD: 0x0500)

Note: This command share the same register as CSI_CONFW. It is in LP command mode when [31:24] = 0x30

S6: 一个tc358746 可以连接多少个camera？ 可以同时连接4个吗？

Parallel to CSI-2 converter

此文档参考资料来自：

TC358746AXBG_748XBG_rev05.pdf

MIPI_D-PHY_Specification_v01-00-00.pdf