lcd_1602

module lcd_pdf(
        clk,lcd_data,
        lcd_rw,lcd_rs,
        lcd_en,rst_n
);

input                        clk;
input                        rst_n;
output    reg    [:]    lcd_data;
output    reg            lcd_rw;  // wirte      L
output    reg            lcd_en;
output    reg            lcd_rs;

//clock 分频
reg    [:]    cnt;
reg                clk_10;
always @(posedge clk or negedge rst_n)
    if(!rst_n)begin
        cnt <= 'd0;
        clk_10 <= 'b0;
    end
    else begin
        if(cnt == )begin
            clk_10 =~ clk_10;
            cnt <= cnt + 'b1;
        end
    end

//shixu
always @(posedge clk_10 or negedge rst_n)
    if(!rst_n)begin
        lcd_rw <= 'b0;
        lcd_en <= 'b0;
    end
    else begin
        case(cnt)
        :begin
                lcd_en <= 'b0;
                lcd_data <= 'h30;
                lcd_rw <= 'b0;
                lcd_rs <= 'b0;
            end
        :begin
                lcd_en <= 'b1;
            end
        :begin
                lcd_en <= 'b0;
                lcd_data <= 'h0c;
                lcd_rw <= 'b0;
                lcd_rs <= 'b0;
            end
        :begin
                lcd_en <= 'b1;
            end
        :begin
                lcd_en <= 'b0;
                lcd_data <= 'h01;
                lcd_rw <= 'b0;
                lcd_rs <= 'b0;
            end
        :begin
                lcd_en <= 'b1;
            end
        :begin
                lcd_en <= 'b0;
                lcd_data <= 'h80;
                lcd_rw <= 'b0;
                lcd_rs <= 'b0;
            end
        :begin
                lcd_en <= 'b1;
            end
        :begin
                lcd_en <= 'b0;
                lcd_data <= 'h30;//字符0
                lcd_rw <= 'b0;
                lcd_rs <= 'b1;
            end
        :begin
                lcd_en <= 'b1;
            end
        default:lcd_en <= 'b0;
        endcase
    end
endmodule

主要还是按照时序图的时间顺序一步步的写，没有上机验证 而且tb在处理很大的数的时候不知道具体咋弄，留下以后解决

//-----------------------------------2-10号修改------------------------------------------//

module fsm_lcd(
        rs,rw,en,data,
        clk,rst_n
);

input        wire        clk;
input        wire        rst_n;
output    reg        rs;    //write_cmd -L  or write_data -H
output    wire        rw;  //write - L
output    reg        en;  //写数据或者写指令 高脉冲
output    reg        [:]        data;

//上电20ms稳定电源
parameter    TIME_20MS = 'd1_0-1;//为了仿真将时间缩短
reg    [:]        cnt_init;
always @(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt_init <= 'd0;
    else if(cnt_init == TIME_20MS)
        cnt_init <= TIME_20MS;
    else
        cnt_init <= cnt_init + 'b1;

//分频  1602为慢速器件，要降低clk频率
parameter    DIV_CNT = 'd5 - 1;//加快仿真速度;
reg    [:]        cnt_div;
reg    clk_500hz;
always @(posedge clk or negedge rst_n)
    if(!rst_n)begin
        cnt_div <= 'd0;
        clk_500hz <= 'd0;
    end
    else if(cnt_div == DIV_CNT)begin
        cnt_div <= 'd0;
        clk_500hz =~ clk_500hz;
    end
    else
        cnt_div <= cnt_div + 'b1;

//fsm
reg        [:]        state;
reg        [:]        cnt_ms;
always @(posedge clk_500hz or negedge rst_n)
    if(!rst_n)begin
        data <= 'd0;
        en <= 'd0;
        rs <= 'd0;
        state <= 'd0;
        cnt_ms <= 'd0;
    end
    else if(cnt_init == TIME_20MS)
        case(state)
        'd0:begin
            data <= 'd0;
            en <= 'd0;
            rs <= 'd0;
            state <= 'd1;
        end
        'd1:begin
            data <= 'h38;  //显示模式
            en   <= 'd0;
            rs   <= 'd0;
            state <= 'd2;
        end
        'd2:
            if(cnt_ms == 'd2)begin
                cnt_ms <= 'd0;
                en <= 'd1;
                rs <= 'd0;
                state <= 'd3;
            end
            else cnt_ms <= cnt_ms + 'b1;
        'd3:begin //0x0c 开显示不显示光标
            data <= 'h0c;
            en <= 'd0;
            rs <= 'd0;
            state <= 'd4;
            end
        'd4:begin
            en <= 'd1;
            state <= 'd5;
            end
        'd5:
            if(cnt_ms == 'd2)begin
                cnt_ms <= 'd0;
                en <= 'd0;
                state <= 'd6;
            end
            else cnt_ms <= cnt_ms + 'b1;
        'd6:begin //0x80  首地址
            en <= 'd0;
            data <= 'h80;
            state <= 'd7;
            end
        'd7:begin
            en <= 'd1;
            state <= 'd8;
            end
        'd8:if(cnt_ms == 3'd2)begin //write_data
            cnt_ms <= 'd0;
            en <= 'd0;
            rs <= 'd1;
            data <= 'h1;
            state <= 'd9;
            end
            else cnt_ms <= cnt_ms + 'b1;
        'd9:begin
            en <= 'd1;
            state <= 'd10;
            end
        'd10:
            if(cnt_ms == 'd2)begin
                cnt_ms <= 'd0;
                en <= 'd0;
                state <= 'd0;
                end
            else cnt_ms <= cnt_ms + 'b1;
        default:state <= 'd0;
    endcase

assign     rw    = 'b0;

endmodule