ICEE-PCIe-PCI-SIG + What + Generations + PCIe6.0@x16@256GB/s

1. PCI-SIG:
   
   https://pcisig.com
2. PCIe Available Specification:
   
   http://pcisig.com/specifications
3. Download the PCIe6.0 Specification
4. Intel PCIe:
5. What is PCIe(Peripheral Component Interconnect express)?

What is PCIe?

Last Updated : 06 Jul, 2022

• PCIe stands for Peripheral Component Interconnect express. It is an interface standard that is used to connect high-speed components. it is a high-bandwidth expansion bus.
• Newer PCIe standards mean a higher-bandwidth connection to GPUs, SSDs, and other peripherals.
  
  All generations of PCIe are backwards compatible, so there's no reason not to upgrade.
• PCIe is available in a different physical configuration(PCIe lanes) which includes x1, x2, x4, x8, x16, x32.
  
  Higer Configuration(More lanes) mean more bandwidth, as well as a longer slot.
  • The motherboard has a number of PCIe slots to connect different components such as GPU(or video cards or graphics cards ), WI-FI cards, SSD (Solid-state drive).
    
    Different motherboards have different types of PCIe slots.
  • commonly used to connect graphics cards and SSDs, as well as peripherals like capture cards and wireless cards.
  • GPUs are usually installed in the top slot, as it has the most bandwidth and,
    
    traditionally, the most direct connection to the CPU.
  • Modern PCIe m.2 SSDs use x4 or higer lanes.

PCIe Generation Comparison:

Bandwidth	Gigatransfer	Frequency	Encoding
PCIe 1.0	8 GB/s	2.5 GT/s	2.5 GHz
PCIe 2.0	16 GB/s	5 GT/s	5.0 GHz
PCIe 3.0	32 GB/s	8 GT/s	8.0 GHz
PCIe 4.0	64 GB/s	16 GT/s	16.0 GHz
PCIe 5.0	128 GB/s	32 GT/s	32.0 GHz
PCIe 6.0	256 GB/s	64 GT/s	64.0 GHz
PCIe 7.0	512 GB/s	128 GT/s	128.0 GHz

Generation of PCIe

Till now six generations of PCIe have been introduced in the market i.e PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, PCIe 6.0 out of these only first four have been debuted in the market.

PCIe 4.0 was first introduced in 2019 by AMD Ryzen 3000-series CPUs.

History

AWG(Arapaho Work Group), initially consisted of Intel engineers, later expanded to include industry partners, draw this standard.

First PCIe was named as High-Speed Interconnect (HSI), then renamed to 3GIO (3rd generation I/O) and finally renamed to PCIe.

• PCIe 1.0a: It was introduced by PCI-SIG in year 2003. It has a per-lane data rate of 250 MB/s and a transfer rate of 2.5 Giga transfers per second (GT/s).
• PCIe 1.1: It was introduced by PCI-SIG in year 2005. It has more clarification and improvement over PCIe 1.0a but * per-lane data rate and transfer rate was unchanged.
• PCIe 2.0: It was introduced by PCI-SIG in year 2007. It doubled the per-lane data rate and transfer rate compared to PCIe 1.0. It has a per-lane data rate of 500MB/s instead of 250 MB/s and a transfer rate of 5GT/s instead of 2.5 Giga transfers per second (GT/s). PCIe 2.0 slots provides backward compatibility with PCIe 1.x cards.
• PCIe 3.0: It was introduced by PCI-SIG in November 2010, after multiple delays. In August 2007, PCI-SIG announced backward compatible with existing PCI Express implementations and a bit rate of 8 Giga transfers per second (GT/s) for PCI Express 3.0. PCI-SIG also announced, a delay in release until Q2 2010 for the final specification for PCI Express 3.0. A number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies were added in PCI Express 3.0 specification It has a per-lane data rate of 984.6MB/s instead of 500MB/s (as in PCIe 2.0) and a transfer rate of 8GT/s instead of 5 GT/s (as in PCIe 2.0).
• PCIe 4.0: It was introduced by PCI-SIG on November 29, 2011. It doubled the per-lane data rate and transfer rate compared to PCIe 3.0. It has a per-lane data rate of 1969MB/s instead of 984.6MB/s (as in PCIe 3.0) and a transfer rate of 16GT/s instead of 8 GT/s (as in PCIe 3.0). PCIe 4.0 provides full backward and forward compatibility.
• PCIe 5.0: PCI Express 5.0 preliminary specification was introduces by PCI-SIG in JUNE, 2017. In a 16-lane configuration Bandwidth was expected to increase to 32 GT/s, yielding 63 GB/s in each direction. The draft was expected to be standardized in 2019. Final PCI-Express 5.0 specification was introduced by PCI-SIG On 29 May 2019. The mass production for PCIe 5.0 is planned to start in 2020.
  
  PCIe 6.0: PCI-SIG announced the development of PCI Express 6.0 specification On June 18, 2019.
  
  It has a target release date of 2021.
  • In a 16-lane configuration bandwidth is expected to increase to 64 GT/s, yielding 128 GB/s in each direction.
  • PAM-4(4-level pulse-amplitude modulation) with low-latency FEC(forward error correction) in place of non-return-to-zero (NRZ) modulation is used in this new standard.
    
    Forward error correction is used to increase data integrity,
    
    PAM-4 is used as line code so that two bits are transferred per transfer which was not provided in the earlier version.
    
    It has 64 GT/s data transfer rate (raw bit rate) and up to 256 GB/s via x16 configuration.

PCIe 7.0 Specification

PCI Express (PCIe) specification has served as the de facto interconnect of choice for nearly two decades and will continue to evolve to meet the needs of the compute continuum.

As was announced at the PCI-SIG Developers Conference 2022, the forthcoming PCIe 7.0 specification is targeted for member release in 2025.

• PCIe 7.0 specification is intended to provide a data rate of 128 GT/s, providing a doubling of the data rate of the PCIe 6.0 specification.
• PCIe 7.0 technology is targeted to be a scalable interconnect solution for data-intensive markets like Artificial Intelligence/Machine Learning, Data Center, HPC, Automotive, IoT, and Military/Aerospace.

PCIe 7.0 Specification Feature Goals

• Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration Utilizing PAM4(Pulse Amplitude Modulation with 4 levels) signaling
• Focusing on maintaining the channel parameters and reach
  
  Continuing to deliver the low-latency and high-reliability targets
• Improving power efficiency
• Maintaining backwards compatibility with all previous generations of PCIe technology

PCIe 7.0 Specification Resources

• Press Release
• FAQ
• Blogs:
  • Announcing the PCIe 7.0 Specification: Doubling the Data Rate to 128 GT/s for the Next Generation of Computing
  • The PCIe 7.0 Specification, Version 0.3 is Now Available to Members
• Infographics:
  • Doubling Bandwidth Graphic
  • Speeds and Feeds Graphic