qnx gpio
in order to set gpio in qnx, you can use
msmgpiotool
# msmgpiotool
gpiotool
usage: gpiotool <command> <gpio> <arg>
PLEASE IGNORE ALTERNATE FUNCTION VALUES , TOOL IS NOT UPDATED WITH CORRECT VALUES FOR
Provides a mechanism to easily view and reconfigure TLMM GPIOs on the command
line.
commands:
dump
info <gpio number>
write <gpio number> <value>
read <gpio>
rawread <gpio>
set-dir <gpio number> <value>
set-drive <gpio number> <value>
set-pull <gpio number> <value>
set-func <gpio number> <value>
enable-irq <gpio number> <value>
clear-irq <gpio>
set-pol <gpio number> <value>
set-trigger <gpio number> <value>
Description:
dump prints the entire GPIO configuration table
info prints the configuration for the specified gpio
set-dir sets the direction when in gpio mode
[] Input, [] Output
set-drive sets the pin drive strength regardless of mode
drive strength = [n] * 2mA ..]
set-pull sets internal pull on the pin regardless of mode
[] No pull [] Pull Down [] Keeper [] Pull Up
for GPIO mode
valid ..]
enable-irq configures the pin as a gpio interrupt source
[] Enable [] Disable
clear-irq clears the pending IRQ status
set-pol sets the interrupt polarity of the gpio
[] Inverted [] Normal
set-trigger sets the irq trigger type
[] Level [] Edge
# # echo 1 >4
# msmgpiotool info 4
100c7ab8 GPIO IN OUT DIR DRIVE PULL ALTERNATE FUNCTION TARGET IRQ POL TRIG STS
----------------------------------------------------------------------------------
100c79b8 4 High High In 2 mA No pull 2 NONE 0 1 Level 0
# ehco 0 >4
#msmgpiotool info 4
100c7ab8 GPIO IN OUT DIR DRIVE PULL ALTERNATE FUNCTION TARGET IRQ POL TRIG STS
----------------------------------------------------------------------------------
100c79b8 4 High Low In 2 mA No pull 2 NONE 0 1 Level 0
具体的定义在X:\qnx_poc\qnx_workspace\hqx1.1-8.1-qnx\3rdparty\boards\core\dalconfig\mojave_v2_8996\config\pin_config.c
/*==============================================================================
PMIC PIN MUXING CONFIGURATION TABLE
DESCRIPTION
This file has the dplmp performance table supported
REFERENCES
Copyright 2015 Qualcomm Technologies Incorporated.
All Rights Reserved.
QUALCOMM Proprietary/GTDR
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header$
when who what, where, why
-------- --- ----------------------------------------------------------
07/29/2015 aneeketp Added Macros and stage column
05/08/2015 knr Updated the configuration based on the MMX2 board review.
04/29/2015 guru First draft created.
===========================================================================*/
#include "gpio_client.h"
#include "pin_config.h"
/*
VIN0: VPH_PWR ( 3.7V )
GPIO01-GPIO08 (VPH_PWR_MPP1)
GPIO09-GPIO22 (VPH_PWR_MPP5)
VIN1: S6 (1.1V) and L19 (3.3V)
GPIO01-GPIO08 (VREG_S6_MPP1)
GPIO09-GPIO22 (VREG_L19_MPP5)
VIN2: S4 1.8 V
GPIO01-GPIO08 (VIN_S4_MPP1)
GPIO09-GPIO22 (VIN_S4_MPP5)
VIN3: L12 (1.8V)
GPIO01-GPIO08 (VREG_L12_MPP1)
GPIO09-GPIO22 (VREG_L12_MPP5)
*/
// Refer to PMIC objective Spec to update values for different pmics
//VOLTAGE_SOURCE
#define PM_GPIO9_TO_GPIO22_VLTG_3V3 PMIC_GPIO_V1
#define PM_GPIO9_TO_GPIO22_VLTG_1V1 PMIC_GPIO_V2
#define PM_GPIO9_TO_GPIO22_VLTG_1V8 PMIC_GPIO_V3
#define PM_GPIO1_TO_GPIO8_VLTG_3V3 PMIC_GPIO_V1
#define PM_GPIO1_TO_GPIO8_VLTG_1V1 PMIC_GPIO_V2
#define PM_GPIO1_TO_GPIO8_VLTG_1V8 PMIC_GPIO_V3
/*
Vio_0: VPH_PWR
MPP01-MPP04 (VPH_PWR_MPP1)
MPP05-MPP08 (VPH_PWR_MPP5)
Vio_1: S6 (1.1V) and L19 (3.3V)
MPP01-MPP04 (VREG_S6_MPP1)
MPP05-MPP08 (VREG_L19_MPP5)
Vio_2: S4 (1.8V)
MPP01-MPP04 (VIN_S4_MPP1)
MPP05-MPP08 (VIN_S4_MPP5)
Vio_3: L12 (1.8V)
MPP01-MPP04 (VREG_L12_MPP1)
MPP05-MPP08 (VREG_L12_MPP5)
*/
#define PM_MPP1_TO_MPP4_VLTG_VPH PMIC_MPP__DLOGIC__LVL_VIO_0
#define PM_MPP1_TO_MPP4_VLTG_1V1 PMIC_MPP__DLOGIC__LVL_VIO_1
// Can use V3 also , which sources from L12 instead of S4. Please use correct value per requirement
#define PM_MPP1_TO_MPP4_VLTG_1V8 PMIC_MPP__DLOGIC__LVL_VIO_2
#define PM_MPP5_TO_MPP8_VLTG_VPH PMIC_MPP__DLOGIC__LVL_VIO_0
#define PM_MPP5_TO_MPP8_VLTG_3V3 PMIC_MPP__DLOGIC__LVL_VIO_1
// Can use V3 also , which sources from L12 instead of S4. Please use correct value per requirement
#define PM_MPP5_TO_MPP8_VLTG_1V8 PMIC_MPP__DLOGIC__LVL_VIO_2
#define PMIC_MPP_DEFAULT_MASK 0xFF
#define IGNORE_MASK 0x0
// The following masks/configs are guidelines and mostly commonly constructed macros for gpio configuration
// Please refer to gpio_client.h and gpio_client_*.h headers for correct macros to be used for more specific use cases
// Use Appropriate VOLTAGE_SOURCE depending on the pmic gpio pin as show above
#define PMIC_GPIO_OUTPUT_DEFAULT(VOLTAGE_SOURCE) PMIC_GPIO_SET_OUTPUT_CONF(VOLTAGE_SOURCE, \
PMIC_GPIO_OUT_BUFFER_CONFIG_CMOS, \
PMIC_GPIO_SOURCE_GND, \
PMIC_GPIO_OUT_BUFFER_HIGH)
#define PMIC_GPIO_INPUT_DEFAULT PMIC_GPIO_SET_INPUT_CONF(PMIC_GPIO_INTERRUPT_POLARITY_NO_INVERT, \
PMIC_GPIO_OUT_BUFFER_CONFIG_CMOS, \
PMIC_GPIO_I_SOURCE_PULL_NO_PULL, \
PMIC_GPIO_SOURCE_GND)
// Use Appropriate VOLTAGE_SOURCE depending on the pmic gpio pin as show above
#define PMIC_MPP_OUTPUT_DEFAULT(VOLTAGE_SOURCE) PMIC_MPP_SET_OUTPUT_CONF(VOLTAGE_SOURCE, \
PMIC_MPP__DLOGIC_OUT__CTRL_LOW)
#define PMIC_MPP_INPUT_DEFAULT(VOLTAGE_SOURCE,DTEST_SELECT) PMIC_MPP_SET_DIGITAL_INPUT_CONF(VOLTAGE_SOURCE, \
DTEST_SELECT)
#define TLMM_GPIO_CFG_MASK_IGNORE 0x0
#define TLMM_GPIO_OUTPUT_DEFAULT GPIO_PIN_CFG(GPIO_OUTPUT,GPIO_NO_PULL,GPIO_STRENGTH_2MA,0)
#define TLMM_GPIO_INPUT_DEFAULT GPIO_PIN_CFG(GPIO_INPUT,GPIO_NO_PULL,GPIO_STRENGTH_2MA,0)
#define INVALID_PIN 0xFFFFFFFF
pin_cfg pin_cfg_table[] =
{
#if 0 //Reference
/*Note: PMIC MPPs and GPIOs are zero indexed when using gpio_client APIs*/
/*PMIC_GPIO PINS CONFIGURATION*/
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unsued_1", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO1_TO_GPIO8_VLTG_3V3), HIGH },
/*pmic_gpio_pin2 -->push button switch for volume up*/
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/vol_up_n", PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_3", PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO1_TO_GPIO8_VLTG_3V3), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/adv7481_rst_n", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO1_TO_GPIO8_VLTG_3V3), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/adv7481_int1_n", PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/adv7481_int2_n", PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/adv7481_int3_n", PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/wlan_en", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO1_TO_GPIO8_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/wlan_3p3_en", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_3V3), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_10", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/vbus_usbss_en1", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_3V3), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_12", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/neu_rst", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/rst", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_15", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_16", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/vbus_ss_det",PMIC_GPIO_SET_INPUT_CONF_MASK, PMIC_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/divclk4", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/divclk4", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/pmic_slb", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_21", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/unused_22", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
/*TLMM PINS CONFIGURATION */
/*SPI - CDP FPGA, Ethernet*/
{(TLMM_MODULE|), , HIGH },
{(TLMM_MODULE|), , IGNORE },
{(TLMM_MODULE|), , HIGH },
{(TLMM_MODULE|), , HIGH },
/*UART - Debug*/
{(TLMM_MODULE|), "/dev/qcgpio/apq_uart_tx", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/apq_uart_rx", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*I2C for DSI/HDMI Bridge Chips*/
{(TLMM_MODULE|), , HIGH },
{(TLMM_MODULE|), , HIGH },
/* SPI - HDMI to Bridge chip (Unused)*/
{(TLMM_MODULE|), "/dev/qcgpio/future_spi_mosi", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/future_spi_miso", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|),"/dev/qcgpio/future_spi_cs_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|),"/dev/qcgpio/future_spi_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_12", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*ds90x_fr_sync*/
{(TLMM_MODULE|), "/dev/qcgpio/ds90x_fr_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_14", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_15", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*uh949_int_n*/
{(TLMM_MODULE|), "/dev/qcgpio/uh949_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*CCI_I2C - CVBS Bridge*/
{(TLMM_MODULE|), "/dev/qcgpio/i2c_cci_sda0",TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/i2c_cci_scl0",TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*CCI_I2C - HDMI_RX*/
{(TLMM_MODULE|), "/dev/qcgpio/i2c_cci_sda1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/i2c_cci_scl1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x_pd", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x_int", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x_link_pass", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT,IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x2_int", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x2_link_pass", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ds90x2_fr_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*I2C - Neutrino*/
{(TLMM_MODULE|), , HIGH },
{(TLMM_MODULE|), , HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_29", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_30", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/hdmi_cec", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*HDMI I2C*/
{(TLMM_MODULE|), "/dev/qcgpio/hdmi_ddc_clock", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/hdmi_ddc_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/hdmi_hot_plug_detect", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie0_rst_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/pcie0_clkreq_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie0_wake", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/sd_card_det_n",TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*APQ to RH850 Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/rh8_apq2rh850", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*SD card write protect*/
{(TLMM_MODULE|), "/dev/qcgpio/dr3_radio_ioexp_int", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*UART - Bluetooth*/
{(TLMM_MODULE|), "/dev/qcgpio/rome_uart_txd", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rome_uart_rxd", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/rome_uart_cts", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rome_uart_rts", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*UART - WLAN GeoFence*/
{(TLMM_MODULE|), "/dev/qcgpio/unused_45", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_46", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_47", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_48", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*SPI - RH850*/
{(TLMM_MODULE|), "/dev/qcgpio/rh8_spi_mosi", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rh8_spi_miso", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/rh8_spi_cs_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rh8_spi_spi_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*APQ to Neutrino Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/neu_apq2ntn_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT,HIGH },
/*PCI_E2 - USB_SS Bridge*/
{(TLMM_MODULE|), "/dev/qcgpio/unused_54", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT,HIGH },
/*I2C - LP4 Reg, GFX Reg, General*/
{(TLMM_MODULE|), "/dev/qcgpio/apq_i2c_sda", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/apq_i2c_scl", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*Forced USB Boot Button*/
{(TLMM_MODULE|), "/dev/qcgpio/forced_usb_boot", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT,IGNORE },
/*I2S - Neutrino*/
{(TLMM_MODULE|), "/dev/qcgpio/quart_scl", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT,IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/quart_ws", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/quart_data0", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/quart_data1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/quart_data2", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/quart_data3", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uh949_rem_init", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcm_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/pcm_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/pcm_din", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcm_dout", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn_clk_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_70", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/adv7533_1_pd", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/adv7533_1_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/adv7533_2_pd2", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/adv7533_2_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/apq_ter_sck", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ter_ws", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ter_d0", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/ter_d1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_79", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/apq_sck_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/apq_sec_ws", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/apq_sec_d0", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT,IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/apq_sec_d1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/mag_sns_reset_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_85", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_86", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_87", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_88", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uh949_pdb", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_90", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_91", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/unused_92", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/unused_93", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_94", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/unused_95", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/unused_96", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc0", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn_clk_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc2", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc3", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/boot_config0", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/boot_config1", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/boot_config2", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/boot_config3", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/uim2_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim2_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim2_reset", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim2_present", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/uim1_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim1_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim1_reset", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/uim1_present", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/unused_113", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_8", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_9", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_10", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
/*Accelerometer Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/int1_accel", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*Gyroscope Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/int2_gyro", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*Magnetometer Data Ready Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/mag_drd", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*ALS needed?*/
{(TLMM_MODULE|), "/dev/qcgpio/int_als", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/unused_121", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*RH850 to APQ Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/rh8_rh8502apq", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
/*Neutrino to APQ Interrupt*/
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn2apq_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn_wake_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/f18_ts_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/apps_boot_from_rom",TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_11", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/apq_rh8_dr_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_13", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/neu_pcie1_rst", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/neu_pcie1_clkreq", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/neu_pcie1_wake", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn2apq_int_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/gsm_tx1_phase_d", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/gsm_tx2_phase_d", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/grfc_15", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe3_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe3_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe4_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe4_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe5_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe5_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/gps_tx_aggressor", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/coex_uart_tx", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/coex_uart_rx", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/rffe2_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe2_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe1_data", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/rffe1_clk", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{ 0xFFFFFFFF,"",0xFFFFFFFF,0xFFFFFFFF}
#endif
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/usb_pwr_0", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_3V3), HIGH },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/neu_rst", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PM_GPIO9_TO_GPIO22_VLTG_1V8), HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/qspi_rfe_mux",TLMM_GPIO_CFG_MASK_IGNORE, TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
// {(TLMM_MODULE|108), "/dev/qcgpio/uim2_present",TLMM_GPIO_CFG_MASK_IGNORE, TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie0_rst_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie0_clkreq_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/neu_ntn_clk_sync", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, HIGH },
{(TLMM_MODULE|), "/dev/qcgpio/pcie2_rst_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie2_clkreq_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie1_rst_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_OUTPUT_DEFAULT, IGNORE },
{(TLMM_MODULE|), "/dev/qcgpio/pcie1_clkreq_n", TLMM_GPIO_CFG_MASK_IGNORE,TLMM_GPIO_INPUT_DEFAULT, IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/wlan_en", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PMIC_GPIO_V2), HIGH},
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/wlan_3p3_en", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PMIC_GPIO_V2), IGNORE },
{(PMIC_GPIO_MODULE|), "/dev/qcgpio/bt_en", PMIC_GPIO_SET_OUTPUT_CONF_MASK, PMIC_GPIO_OUTPUT_DEFAULT(PMIC_GPIO_V2), IGNORE },
{ 0xFFFFFFFF,"",0xFFFFFFFF,0xFFFFFFFF}
};
pin_config.c
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