16Khz音频定时触发采样DMA存储过程

一、AD Setting

1、Calibration (ADCAL)

2、设定ADC Chennel与SCANDIR等，在低功耗应用方案，选择PCLK/4，并设置SMP(tCONV = Sampling time + 12.5 x ADC clock cycles)

3、AD设置为Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT=0 in the ADC_CFGR1 register.
Conversion is started by either:
● Setting the ADSTART bit in the ADC_CR register
● Hardware trigger event
Inside the sequence, after each conversion is complete:
● The converted data are stored in the 16-bit ADC_DR register
● The EOC (end of conversion) flag is set
● An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
● The EOSEQ (end of sequence) flag is set
● An interrupt is generated if the EOSEQIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.

4、Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART=1.
When ADSTART is set, the conversion:
● Starts immediately if EXTEN = 0x0 (software trigger)
● At the next active edge of the selected hardware trigger if EXTEN  0x0
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART=0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
● In single mode with software trigger (CONT=0, EXTSEL=0x0)
– At any end of conversion sequence (EOSEQ=1)
● In all cases (CONT=x, EXTSEL=x)
– After execution of the ADSTP procedure invoked by software (see
Section 12.4.11: Stopping an ongoing conversion (ADSTP) on page 179.
Note: 1 In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the
EOSEQ flag is set because the sequence is automatically relaunched.
2 When hardware trigger is selected in single mode (CONT=0 and EXTSEL  0x00),
ADSTART is not cleared by hardware when the EOSEQ flag is set. This avoids the need for
software having to set the ADSTART bit again and ensures the next trigger event is not
missed.

5、Conversion on external trigger and trigger polarity (EXTSEL,EXTEN)

EXTEN[1:0]=01  -> rising edge

EXTSEL[2:0]=100->TIM15_TRGO

6、RES设置解析度12bit与数据右对齐方式

7、Managing converted data using the DMA ==>DMAEN=1，DMA circular mode (DMACFG=1)

Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA
request is generated after the conversion of each channel. This allows the transfer of the

converted data from the ADC_DR register to the destination location selected by the
software.

二、DMA Setting

The following sequence should be followed to configure a DMA channelx (where x is the
channel number).
1. Set the peripheral register address in the DMA_CPARx register. The data will be
moved from/ to this address to/ from the memory after the peripheral event.
2. Set the memory address in the DMA_CMARx register. The data will be written to or
read from this memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5. Configure data transfer direction, circular mode, peripheral & memory incremented
mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register
6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral
connected on the channel.

三、TIM SETTING

1、设置TIM15为16Khz溢出，并设置URS=0，UDIS=0=>使能UEV event （不需配置更新中断）；

2、设置MMS[2:0]=010

Update - The update event is selected as trigger output (TRGO).

3、使能TIM

OK!

注：

1、相应Clk需Enable；

2、DMA的buf满了之后会触发中断，从中获取数据；