FPGA开发（1）

 `timescale  ns /  ns
 module system_ctrl
 (
     //globol clock
     input                clk,
     input                rst_n,

     //synced signal
     output                 clk_ref,    //clock output
     output                 sys_rst_n    //system reset
 );

 //----------------------------------------------
 //rst_n sync, only controlled by the main clk
 reg     rst_nr1, rst_nr2;
 always @(posedge clk)
 begin
     if(!rst_n)
         begin
         rst_nr1 <= 'b0;
         rst_nr2 <= 'b0;
         end
     else
         begin
         rst_nr1 <= 'b1;
         rst_nr2 <= rst_nr1;
         end
 end

 //----------------------------------
 //component instantiation for system_delay
 wire    delay_done;    //system init delay has done
 system_init_delay
 #(
     .SYS_DELAY_TOP    ('d2500000)
 //    .SYS_DELAY_TOP    (24'd256)    //Just for test
 )
 u_system_init_delay
 (
     //global clock
     .clk        (clk),
     .rst_n        ('b1),            //It don't depend on rst_n when power up
     //system interface
     .delay_done    (delay_done)
 );

 assign    clk_ref = clk;
 assign    sys_rst_n = rst_nr2 & delay_done;    //active High

 endmodule