基于Verilog HDL 的数字电压表设计

　　本次实验是在“基于Verilog HDL的ADC0809CCN数据采样”实验上进一步改进，利用ADC0809采集到的8位数据，进行BCD编码，以供查表方式相加进行显示，本次实验用三位数码管。

　　ADC0809的8位数数据BCD编码方式，低四位与高四位分开进行编码，其对应值我也是从网上得来的，具体对应值请看代码，编完码得到12位宽的数据后，对两个编码进行相加，如代码中的cout[11:0] = L[11:0] + H[11:0],这里注意，高四位[11:8]、中四位[7:4]、低四位[3:0]。

假如ADC0809得到的数据是8'hb4,从代码中可以看到，低四位4'h4:  L <= 12'h008;高四位4'hb:  H <= 12'h352;，H+L = 12’h35A,低位为A，大于9，向中位产生进位C0= 1，其低位得加6得到0，故cout[11:0]=12'h360，电压也就是3.60V,然后把360送给数码管进行显示。同理如果中位相加大于9也得向高位进位C1，此时的中位要变为加6后的值。

代码实现：

display_control.v

 module  display_control(
                         //input
                         sys_clk,//27MHZ
                         rst_n,
                         seg_data,//ADC0809传送进来的数据

                         //output
                         slec_wei,
                         slec_duan
                     );
 input rst_n;
 input [:] seg_data;
 input sys_clk;

 output [:] slec_wei;
 output [:] slec_duan;

 /*****************************************/
 parameter     SEG_NUM0     = 'h3f,
             SEG_NUM1     = 'h06,
             SEG_NUM2     = 'h5b,
             SEG_NUM3     = 'h4f,
             SEG_NUM4     = 'h66,
             SEG_NUM5     = 'h6d,
             SEG_NUM6     = 'h7d,
             SEG_NUM7     = 'h07,
             SEG_NUM8     = 'h7f,
             SEG_NUM9     = 'h6f,
             SEG_NUMa    = 'h77,
             SEG_NUMb    = 'h7c,
             SEG_NUMc    = 'h39,
             SEG_NUMd    = 'h5e,
             SEG_NUMe    = 'h79,
             SEG_NUMf    = 'h71;
 parameter   T5MS         = 'd134_999;
 /************************************/
 //低四位BCD编码
 reg [:] L;
 always @ (posedge sys_clk)
     case(seg_data[:]) //L = n * 12'h002(n=1、2、3、、f)
         'h1:        L <= 12'h002;
         'h2:        L <= 12'h004;
         'h3:        L <= 12'h006;
         'h4:        L <= 12'h008;
         'h5:        L <= 12'h010;
         'h6:        L <= 12'h012;
         'h7:        L <= 12'h014;
         'h8:        L <= 12'h016;
         'h9:        L <= 12'h018;
         'ha:        L <= 12'h020;
         'hb:        L <= 12'h022;
         'hc:        L <= 12'h024;
         'hd:        L <= 12'h026;
         'he:        L <= 12'h028;
         'hf:        L <= 12'h030;
         default :    L <= 'h000;
     endcase
 /************************************/
 //高四位BCD编码
 reg [:] H;
 always @ (posedge sys_clk)
     case(seg_data[:])  //H = n * 12'h032(n=1、2、3、、f)
         'h1:        H <= 12'h032;  //12'b0000_0011_0010;
         'h2:        H <= 12'h064;  //12'b0000_0110_0100;
         'h3:        H <= 12'h096;  //12'b0000_1001_0110;
         'h4:        H <= 12'h128;  //12'b0001_0010_1000;
         'h5:        H <= 12'h160;  //12'b0001_0110_0000;
         'h6:        H <= 12'h192;  //12'b0001_1001_0010;
         'h7:        H <= 12'h224;  //12'b0010_0010_0100;
         'h8:        H <= 12'h256;  //12'b0010_0101_0110;
         'h9:        H <= 12'h288;  //12'b0010_1000_1000;
         'ha:        H <= 12'h320;  //12'b0011_0010_0000;
         'hb:        H <= 12'h352;  //12'b0011_0101_0010;
         'hc:        H <= 12'h384;  //12'b0011_1000_0100;
         'hd:        H <= 12'h416;  //12'b0100_0001_0110;
         'he:        H <= 12'h448;  //12'b0100_0100_1000;
         'hf:        H <= 12'h480;  //12'b0100_1000_0000;
         default :     H <= 'h000;  //12'b0000_0000_0000;
     endcase
 /************************************/
 //判断低四位是否大于9并进位
 reg c0;
 always @ (posedge sys_clk)
 begin
     if(H[:] + L[:] > 'd9)
         c0 <= ;
     else
         c0 <= ;
 end
 /************************************/
 //判断中间四位是否大于9并进位
 reg c1;
 always @(posedge sys_clk)
 begin
     if(H[:] + L[:] > 'd9)
         c1 <= ;
     else
         c1 <= ;
 end
 /***********************************************/
 //对进位进行计算,中四位减去2，低四位加上1，是为了校准显示电压与实测电压更为接近，根据情况而定
 reg [:] cout;
 always @(c1 or c0)
 begin
     case({c1,c0})
         'b00: begin
             cout[:] <= H[:] + L[:];
             cout[:] <= H[:] + L[:] - 'd2;//减去4'd2是为了校准显示电压,与实际测试更为接近
             cout[:] <= H[:] + L[:] + 'd1;//减去1'd1是为了校准显示电压,与实际测试更为接近
         end 

         'b01: begin
             if((H[:] + L[:] + 'b0001) > 9) begin
                 cout[:] <= H[:] + L[:] + 'b0001;
                 cout[:] <= H[:] + L[:] + 'b0111 - 4'd2;//加上6并加上来自低位上的进位
                 cout[:] <= H[:] + L[:]+ 'b0110 + 1'd1;//加上6
             end
             else begin
                 cout[:] <= H[:] + L[:];
                 cout[:] <= H[:] + L[:] + 'b0001 - 4'd2;
                 cout[:] <= H[:] + L[:] + 'b0110 + 1'd1;
             end
         end

         'b10:begin
             cout[:] <= H[:] + L[:] + 'b0001;
             cout[:] <= H[:] + L[:] + 'b0110 - 4'd2;
             cout[:] <= H[:] + L[:] + 'd1;
         end  

         'b11:begin
             cout[:] <= H[:] + L[:] + 'b0001;
             cout[:] <= H[:] + L[:] + 'b0110 - 4'd2;
             cout[:] <= H[:] + L[:] + 'b0110 + 1'd1;
         end
     endcase
 end

 /**********************************************/
 //5ms计数器
 reg [:] cnt;
 always @(posedge sys_clk or negedge rst_n)
 if(!rst_n)
     cnt <= 'd0;
 else if(cnt == T5MS)
     cnt <= 'd0;
 else
     cnt <= cnt + 'b1;
 /**********************************************/
 //通过移位方式进行流水工作，定时开关
 reg [:] slec_wei_temp;
 always @(posedge sys_clk or negedge rst_n)
     if(!rst_n) begin
         slec_wei_temp <= 'd011;
     end
     else if(cnt == T5MS) begin
         if(slec_wei_temp == 'b110)
             slec_wei_temp <= 'b011;
         else
             slec_wei_temp <= {'b1,slec_wei_temp[2:1]};
     end

 assign slec_wei = {'b1,slec_wei_temp};
 /*****************************************/
 reg [:] data0;
 always @ (posedge sys_clk)
 case(cout[:])    //进行编码 高
     'h0: data0 <= SEG_NUM0;
     'h1: data0 <= SEG_NUM1;
     'h2: data0 <= SEG_NUM2;
     'h3: data0 <= SEG_NUM3;
     'h4: data0 <= SEG_NUM4;
     'h5: data0 <= SEG_NUM5;
     'h6: data0 <= SEG_NUM6;
     'h7: data0 <= SEG_NUM7;
     'h8: data0 <= SEG_NUM8;
     'h9: data0 <= SEG_NUM9;
     default:data0 <= SEG_NUM0;
 endcase
 /*****************************************/
 reg [:] data1;
 always @ (posedge sys_clk)
 case(cout[:])    //进行编码  中
     'h0: data1 <= SEG_NUM0;
     'h1: data1 <= SEG_NUM1;
     'h2: data1 <= SEG_NUM2;
     'h3: data1 <= SEG_NUM3;
     'h4: data1 <= SEG_NUM4;
     'h5: data1 <= SEG_NUM5;

     'h6: data1 <= SEG_NUM6;
     'h7: data1 <= SEG_NUM7;
     'h8: data1 <= SEG_NUM8;
     'h9: data1 <= SEG_NUM9;
     default:data1 <= SEG_NUM0;
 endcase
 /*****************************************/
 reg [:] data2;
 always @ (posedge sys_clk)
 case(cout[:])    //进行编码  低
     'h0: data2 <= SEG_NUM0;
     'h1: data2 <= SEG_NUM1;
     'h2: data2 <= SEG_NUM2;
     'h3: data2 <= SEG_NUM3;
     'h4: data2 <= SEG_NUM4;
     'h5: data2 <= SEG_NUM5;
     'h6: data2 <= SEG_NUM6;
     'h7: data2 <= SEG_NUM7;
     'h8: data2 <= SEG_NUM8;
     'h9: data2 <= SEG_NUM9;
     default:data2 <= SEG_NUM0;
 endcase
 /***********************************************/
 reg [:] num;
 always @ (posedge sys_clk or negedge rst_n)
 if(!rst_n)
     num <= 'd0;
 else if(cnt == T5MS)
     num <= num + 'b1;
 else if(num == 'd3)
     num <= 'd0;
 /***********************************************/
 reg [:] slec_duan;
 always @ (posedge sys_clk)
 case(num)
     'd0: slec_duan <= data0;
     'd1: slec_duan <= data1;
     'd2: slec_duan <= data2;
 endcase

 endmodule 

adc0809_control.v模块和adc0809_top模块请看基于Verilog HDL的ADC0809CCN数据采样中的代码。

当代码写完之后，发现显示的数据与实际电压有点偏差，高了0.2V左右，后来我测试了一下ADC0809的工作电压是4.8V，不是5V，我想可能是因为跟这个参考电压有关，为了让显示的数据与实际测试尽量接近，可以在代码中进行校准，我在中四位cout[7:4]减2，低cout[3:0]加1，其结果还是比较接近实际值。