Glitch-free clock switch

　　With multi-frequency clocks being used in today’s devices, it's necessary to switch the source of a clock while the device is running.

1　　Problem 

　　The two clock frequencies can be totally unrelated to each other or they can be multiples of each other.

　　In either case, there is a chance of generating a glitch on the clock line at the time of the switch. A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others.

　　　　

2　　Solution

　　1)　　Related clock sources - source clocks are multiples of each other

　　

　　　　Registering select signal at negative-edge of the clock guarantees that no changes occur at the output while either of the clocks is at high level, thus protecting against chopping the output clock. Feedback from one clock's selection to the other enables the switch to wait for de-selection of the Current Clock before starting the propagation of the Next Clock, avoiding any glitches.

　　2)　　Unrelated clock sources

　　

　　Protection is provided against meta-stability by adding one extra stage of positive-edge flop for each of the clock sources. The positive-edge flop in each of the selection paths, along with the existing negative-edge flop, guards against potential meta-stability, which may be caused by asynchronous SELECT signal or asynchronous feedback from one clock domain to the other.

　　A synchronizer is simply two stages of flip flops, where the first stage helps stabilize data by latching it and later passing it on to the next stage to be interpreted by rest of the circuit.