uboot 2013.01 代码简析(2)第一阶段初始化

uboot执行"make smdk2410_config"之后就可以进行编译了，可以执行make命令进行编译，

因为整个输出太长，我仅仅列出部分最关键的输出(部分我不关心的内容直接用......代替)：

arm-linux-gcc ....... < u-boot-2013.01./arch/arm/cpu/u-boot.lds >u-boot.lds

arm-linux-ld  -pie -T u-boot.lds -Bstatic -Ttext 0x0 $UNDEF_LST arch/arm/cpu/arm920t/start.o --start-group api/libapi.o arch/arm/cpu/arm920t/libarm920t.o arch/arm/cpu/arm920t/s3c24x0/libs3c24x0.o arch/arm/lib/libarm.o board/samsung/common/libsamsung.o common/libcommon.o disk/libdisk.o drivers/bios_emulator/libatibiosemu.o drivers/block/libblock.o drivers/dfu/libdfu.o drivers/dma/libdma.o drivers/fpga/libfpga.o drivers/gpio/libgpio.o drivers/hwmon/libhwmon.o drivers/i2c/libi2c.o drivers/input/libinput.o drivers/misc/libmisc.o drivers/mmc/libmmc.o drivers/mtd/libmtd.o drivers/mtd/nand/libnand.o drivers/mtd/onenand/libonenand.o drivers/mtd/spi/libspi_flash.o drivers/mtd/ubi/libubi.o drivers/net/libnet.o drivers/net/phy/libphy.o drivers/pci/libpci.o drivers/pcmcia/libpcmcia.o drivers/power/battery/libbattery.o drivers/power/fuel_gauge/libfuel_gauge.o drivers/power/libpower.o drivers/power/pmic/libpmic.o drivers/rtc/librtc.o drivers/serial/libserial.o drivers/sound/libsound.o drivers/spi/libspi.o drivers/twserial/libtws.o drivers/usb/eth/libusb_eth.o drivers/usb/gadget/libusb_gadget.o drivers/usb/host/libusb_host.o drivers/usb/musb-new/libusb_musb-new.o drivers/usb/musb/libusb_musb.o drivers/usb/phy/libusb_phy.o drivers/usb/ulpi/libusb_ulpi.o drivers/video/libvideo.o drivers/watchdog/libwatchdog.o fs/cbfs/libcbfs.o fs/cramfs/libcramfs.o fs/ext4/libext4fs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o fs/libfs.o fs/reiserfs/libreiserfs.o fs/ubifs/libubifs.o fs/yaffs2/libyaffs2.o fs/zfs/libzfs.o lib/libfdt/libfdt.o lib/libgeneric.o lib/lzma/liblzma.o lib/lzo/liblzo.o lib/zlib/libz.o net/libnet.o post/libpost.o test/libtest.o board/samsung/smdk2410/libsmdk2410.o --end-group /home/host/prac/u-boot-2013.01.01/arch/arm/lib/eabi_compat.o  -L /home/host/soft/FriendlyARM/toolschain/4.4.3/bin/../lib/gcc/arm-none-linux-gnueabi/4.4.3 -lgcc -Map u-boot.map -o u-boot

从这两行输出可以知道，先由arch/arm/cpu/u-boot.lds在当前文件夹下生成u-boot.lds，然后在用生成的u-boot.lds对前面编译过程中生成的目标文件和静态库进行链接。

另外还需要注意的是arm-linux-ld的一些选项的含义：

-pie 用于生成“位置无关代码”
-T u-boot.lds 使用u-boot.lds来作为链接脚本
-Bsharable  生成共享库
-Ttext 0x0 指定代码段的初始地址为0
--start-group和--end-group 用于标志一个组的开始和结束（用于多个目标文件和库文件中都存在相互依赖关系，可以多次执行依赖查找）
-Map u-boot.map 生成Map文件，其名称为u-boot.map

生成的u-boot.lds内容如下：

 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
  . = 0x00000000;
  . = ALIGN();
  .text :
  {
   __image_copy_start = .;
   arch/arm/cpu/arm920t/start.o (.text*)
   *(.text*)
  }
  . = ALIGN();
  .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  . = ALIGN();
  .data : {
   *(.data*)
  }
  . = ALIGN();
  . = .;
  . = ALIGN();
  .u_boot_list : {
 _u_boot_list__start = .;
 _u_boot_list_cmd__start = .;
 *(SORT(.u_boot_list.cmd.*));
 _u_boot_list_cmd__end = .;
 _u_boot_list_env_clbk__start = .;
 *(SORT(.u_boot_list.env_clbk.*));
 _u_boot_list_env_clbk__end = .;
 *(SORT(.u_boot_list.*));
 _u_boot_list__end = .;
  }
  . = ALIGN();
  __image_copy_end = .;
  .rel.dyn : {
   __rel_dyn_start = .;
   *(.rel*)
   __rel_dyn_end = .;
  }
  .dynsym : {
   __dynsym_start = .;
   *(.dynsym)
  }
  _end = .;
  . = ALIGN();
  .mmutable : {
   *(.mmutable)
  }
  .bss __rel_dyn_start (OVERLAY) : {
   __bss_start = .;
   *(.bss*)
    . = ALIGN();
   __bss_end__ = .;
  }
  /DISCARD/ : { *(.dynstr*) }
  /DISCARD/ : { *(.dynamic*) }
  /DISCARD/ : { *(.plt*) }
  /DISCARD/ : { *(.interp*) }
  /DISCARD/ : { *(.gnu*) }
 }

从这个链接脚本可以知道，代码段中最开始是arch/arm/cpu/arm920t/start.o(由arch/arm/cpu/arm920t/start.S编译而成），
start.o之后才是其他的目标文件对应的代码。

arch/arm/cpu/arm920t/start.S内容如下：

 /*
  *  armboot - Startup Code for ARM920 CPU-core
  *
  *  Copyright (c)     Marius Gröger <mag@sysgo.de>
  *  Copyright (c)     Alex Züpke <azu@sysgo.de>
  *  Copyright (c)     Gary Jennejohn <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.,  Temple Place, Suite , Boston,
  * MA - USA
  */

 #include <asm-offsets.h>
 #include <common.h>
 #include <config.h>

 /*
  *************************************************************************
  *
  * Jump vector table as in table . in []
  *
  *************************************************************************
  */

 .globl _start
 _start:    b    start_code
     ldr    pc, _undefined_instruction
     ldr    pc, _software_interrupt
     ldr    pc, _prefetch_abort
     ldr    pc, _data_abort
     ldr    pc, _not_used
     ldr    pc, _irq
     ldr    pc, _fiq

 _undefined_instruction:    .word undefined_instruction
 _software_interrupt:    .word software_interrupt
 _prefetch_abort:    .word prefetch_abort
 _data_abort:        .word data_abort
 _not_used:        .word not_used
 _irq:            .word irq
 _fiq:            .word fiq

     .balignl ,0xdeadbeef

 /*
  *************************************************************************
  *
  * Startup Code (called from the ARM reset exception vector)
  *
  * do important init only if we don't start from memory!
  * relocate armboot to ram
  * setup stack
  * jump to second stage
  *
  *************************************************************************
  */

 .globl _TEXT_BASE
 _TEXT_BASE:
     .word    CONFIG_SYS_TEXT_BASE

 /*
  * These are defined in the board-specific linker script.
  * Subtracting _start from them lets the linker put their
  * relative position in the executable instead of leaving
  * them null.
  */
 .globl _bss_start_ofs
 _bss_start_ofs:
     .word __bss_start - _start

 .globl _bss_end_ofs
 _bss_end_ofs:
     .word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
     .word _end - _start

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
     .word    0x0badc0de

 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
     .word 0x0badc0de
 #endif

 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
     .word    0x0badc0de

 /*
  * the actual start code
  */

 start_code:
     /*
      * set the cpu to SVC32 mode
      */
     mrs    r0, cpsr
     bic    r0, r0, #0x1f
     orr    r0, r0, #0xd3
     msr    cpsr, r0

 #if    defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
     /*
      * relocate exception table
      */
     ldr    r0, =_start
     ldr    r1, =0x0
     mov    r2, #16
 copyex:
     subs    r2, r2, #1
     ldr    r3, [r0], #4
     str    r3, [r1], #4
     bne    copyex
 #endif

 #ifdef CONFIG_S3C24X0
     /* turn off the watchdog */

 # if defined(CONFIG_S3C2400)
 #  define pWTCON    0x15300000
 #  define INTMSK    0x14400008    /* Interrupt-Controller base addresses */
 #  define CLKDIVN    0x14800014    /* clock divisor register */
 #else
 #  define pWTCON    0x53000000
 #  define INTMSK    0x4A000008    /* Interrupt-Controller base addresses */
 #  define INTSUBMSK    0x4A00001C
 #  define CLKDIVN    0x4C000014    /* clock divisor register */
 # endif

     ldr    r0, =pWTCON
     mov    r1, #0x0
     str    r1, [r0]

     /*
      * mask all IRQs by setting all bits in the INTMR - default
      */
     mov    r1, #0xffffffff
     ldr    r0, =INTMSK
     str    r1, [r0]
 # if defined(CONFIG_S3C2410)
     ldr    r1, =0x3ff
     ldr    r0, =INTSUBMSK
     str    r1, [r0]
 # endif

     /* FCLK:HCLK:PCLK = 1:2:4 */
     /* default FCLK is 120 MHz ! */
     ldr    r0, =CLKDIVN
     mov    r1, #3
     str    r1, [r0]
 #endif    /* CONFIG_S3C24X0 */

     /*
      * we do sys-critical inits only at reboot,
      * not when booting from ram!
      */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
     bl    cpu_init_crit
 #endif

     bl    _main

 /*------------------------------------------------------------------------------*/

 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  */
     .globl    relocate_code
 relocate_code:
     mov    r4, r0    /* save addr_sp */
     mov    r5, r1    /* save addr of gd */
     mov    r6, r2    /* save addr of destination */

     adr    r0, _start
     cmp    r0, r6
     moveq    r9, #0        /* no relocation. relocation offset(r9) = 0 */
     beq    relocate_done        /* skip relocation */
     mov    r1, r6            /* r1 <- scratch for copy_loop */
     ldr    r3, _bss_start_ofs
     add    r2, r0, r3        /* r2 <- source end address        */

 copy_loop:
     ldmia    r0!, {r9-r10}        /* copy from source address [r0]    */
     stmia    r1!, {r9-r10}        /* copy to   target address [r1]    */
     cmp    r0, r2            /* until source end address [r2]    */
     blo    copy_loop

 #ifndef CONFIG_SPL_BUILD
     /*
      * fix .rel.dyn relocations
      */
     ldr    r0, _TEXT_BASE        /* r0 <- Text base */
     sub    r9, r6, r0        /* r9 <- relocation offset */
     ldr    r10, _dynsym_start_ofs    /* r10 <- sym table ofs */
     add    r10, r10, r0        /* r10 <- sym table in FLASH */
     ldr    r2, _rel_dyn_start_ofs    /* r2 <- rel dyn start ofs */
     add    r2, r2, r0        /* r2 <- rel dyn start in FLASH */
     ldr    r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
     add    r3, r3, r0        /* r3 <- rel dyn end in FLASH */
 fixloop:
     ldr    r0, [r2]        /* r0 <- location to fix up, IN FLASH! */
     add    r0, r0, r9        /* r0 <- location to fix up in RAM */
     ldr    r1, [r2, #4]
     and    r7, r1, #0xff
     cmp    r7, #23            /* relative fixup? */
     beq    fixrel
     cmp    r7, #2            /* absolute fixup? */
     beq    fixabs
     /* ignore unknown type of fixup */
     b    fixnext
 fixabs:
     /* absolute fix: set location to (offset) symbol value */
     mov    r1, r1, LSR #4        /* r1 <- symbol index in .dynsym */
     add    r1, r10, r1        /* r1 <- address of symbol in table */
     ldr    r1, [r1, #4]        /* r1 <- symbol value */
     add    r1, r1, r9        /* r1 <- relocated sym addr */
     b    fixnext
 fixrel:
     /* relative fix: increase location by offset */
     ldr    r1, [r0]
     add    r1, r1, r9
 fixnext:
     str    r1, [r0]
     add    r2, r2, #8        /* each rel.dyn entry is 8 bytes */
     cmp    r2, r3
     blo    fixloop
 #endif

 relocate_done:

     mov    pc, lr

 _rel_dyn_start_ofs:
     .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
     .word __rel_dyn_end - _start
 _dynsym_start_ofs:
     .word __dynsym_start - _start

     .globl    c_runtime_cpu_setup
 c_runtime_cpu_setup:

     mov    pc, lr

 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */

 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
     /*
      * flush v4 I/D caches
      */
     mov    r0, #0
     mcr    p15, 0, r0, c7, c7, 0    /* flush v3/v4 cache */
     mcr    p15, 0, r0, c8, c7, 0    /* flush v4 TLB */

     /*
      * disable MMU stuff and caches
      */
     mrc    p15, 0, r0, c1, c0, 0
     bic    r0, r0, #0x00002300    @ clear bits 13, 9:8 (--V- --RS)
     bic    r0, r0, #0x00000087    @ clear bits 7, 2:0 (B--- -CAM)
     orr    r0, r0, #0x00000002    @ set bit 2 (A) Align
     orr    r0, r0, #0x00001000    @ set bit 12 (I) I-Cache
     mcr    p15, 0, r0, c1, c0, 0

     /*
      * before relocating, we have to setup RAM timing
      * because memory timing is board-dependend, you will
      * find a lowlevel_init.S in your board directory.
      */
     mov    ip, lr

     bl    lowlevel_init

     mov    lr, ip
     mov    pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */

 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE    72

 #define S_OLD_R0    68
 #define S_PSR        64
 #define S_PC        60
 #define S_LR        56
 #define S_SP        52

 #define S_IP        48
 #define S_FP        44
 #define S_R10        40
 #define S_R9        36
 #define S_R8        32
 #define S_R7        28
 #define S_R6        24
 #define S_R5        20
 #define S_R4        16
 #define S_R3        12
 #define S_R2        8
 #define S_R1        4
 #define S_R0        0

 #define MODE_SVC    0x13
 #define I_BIT        0x80

 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */

     .macro    bad_save_user_regs
     sub    sp, sp, #S_FRAME_SIZE
     stmia    sp, {r0 - r12}            @ Calling r0-r12
     ldr    r2, IRQ_STACK_START_IN
     ldmia    r2, {r2 - r3}            @ get pc, cpsr
     add    r0, sp, #S_FRAME_SIZE        @ restore sp_SVC

     add    r5, sp, #S_SP
     mov    r1, lr
     stmia    r5, {r0 - r3}            @ save sp_SVC, lr_SVC, pc, cpsr
     mov    r0, sp
     .endm

     .macro    irq_save_user_regs
     sub    sp, sp, #S_FRAME_SIZE
     stmia    sp, {r0 - r12}            @ Calling r0-r12
     add    r7, sp, #S_PC
     stmdb    r7, {sp, lr}^            @ Calling SP, LR
     str    lr, [r7, #0]            @ Save calling PC
     mrs    r6, spsr
     str    r6, [r7, #4]            @ Save CPSR
     str    r0, [r7, #8]            @ Save OLD_R0
     mov    r0, sp
     .endm

     .macro    irq_restore_user_regs
     ldmia    sp, {r0 - lr}^            @ Calling r0 - lr
     mov    r0, r0
     ldr    lr, [sp, #S_PC]            @ Get PC
     add    sp, sp, #S_FRAME_SIZE
     /* return & move spsr_svc into cpsr */
     subs    pc, lr, #4
     .endm

     .macro get_bad_stack
     ldr    r13, IRQ_STACK_START_IN        @ setup our mode stack

     str    lr, [r13]            @ save caller lr / spsr
     mrs    lr, spsr
     str    lr, [r13, #4]

     mov    r13, #MODE_SVC            @ prepare SVC-Mode
     @ msr    spsr_c, r13
     msr    spsr, r13
     mov    lr, pc
     movs    pc, lr
     .endm

     .macro get_irq_stack            @ setup IRQ stack
     ldr    sp, IRQ_STACK_START
     .endm

     .macro get_fiq_stack            @ setup FIQ stack
     ldr    sp, FIQ_STACK_START
     .endm

 /*
  * exception handlers
  */
     .align  5
 undefined_instruction:
     get_bad_stack
     bad_save_user_regs
     bl    do_undefined_instruction

     .align    5
 software_interrupt:
     get_bad_stack
     bad_save_user_regs
     bl    do_software_interrupt

     .align    5
 prefetch_abort:
     get_bad_stack
     bad_save_user_regs
     bl    do_prefetch_abort

     .align    5
 data_abort:
     get_bad_stack
     bad_save_user_regs
     bl    do_data_abort

     .align    5
 not_used:
     get_bad_stack
     bad_save_user_regs
     bl    do_not_used

 #ifdef CONFIG_USE_IRQ

     .align    5
 irq:
     get_irq_stack
     irq_save_user_regs
     bl    do_irq
     irq_restore_user_regs

     .align    5
 fiq:
     get_fiq_stack
     /* someone ought to write a more effiction fiq_save_user_regs */
     irq_save_user_regs
     bl    do_fiq
     irq_restore_user_regs

 #else

     .align    5
 irq:
     get_bad_stack
     bad_save_user_regs
     bl    do_irq

     .align    5
 fiq:
     get_bad_stack
     bad_save_user_regs
     bl    do_fiq

 #endif

40行是代码的入口：

.globl _start
_start:    b    start_code

然后跳转到start_code处：

start_code:
    /*
     * set the cpu to SVC32 mode
     */
    mrs    r0, cpsr
    bic    r0, r0, #0x1f
    orr    r0, r0, #0xd3
    msr    cpsr, r0

#if    defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
    /*
     * relocate exception table
     */
    ldr    r0, =_start
    ldr    r1, =0x0
    mov    r2, #
copyex:
    subs    r2, r2, #
    ldr    r3, [r0], #
    str    r3, [r1], #
    bne    copyex
#endif

#ifdef CONFIG_S3C24X0
    /* turn off the watchdog */

# if defined(CONFIG_S3C2400)
#  define pWTCON    0x15300000
#  define INTMSK    0x14400008    /* Interrupt-Controller base addresses */
#  define CLKDIVN    0x14800014    /* clock divisor register */
#else
#  define pWTCON    0x53000000
#  define INTMSK    0x4A000008    /* Interrupt-Controller base addresses */
#  define INTSUBMSK    0x4A00001C
#  define CLKDIVN    0x4C000014    /* clock divisor register */
# endif

    ldr    r0, =pWTCON
    mov    r1, #0x0
    str    r1, [r0]

    /*
     * mask all IRQs by setting all bits in the INTMR - default
     */
    mov    r1, #0xffffffff
    ldr    r0, =INTMSK
    str    r1, [r0]
# if defined(CONFIG_S3C2410)
    ldr    r1, =0x3ff
    ldr    r0, =INTSUBMSK
    str    r1, [r0]
# endif

    /* FCLK:HCLK:PCLK = :: */
    /* default FCLK is  MHz ! */
    ldr    r0, =CLKDIVN
    mov    r1, #
    str    r1, [r0]
#endif    /* CONFIG_S3C24X0 */

    /*
     * we do sys-critical inits only at reboot,
     * not when booting from ram!
     */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif

    bl    _main

前面几行代码将切换到svc32模式。

之后会判断是否配置了CONFIG_AT91RM9200DK或者CONFIG_AT91RM9200EK，

而从include/configs/smdk2410.h文件中没有这样的配置，所以这几行代码不被执行。

然后会判断是否定义了CONFIG_S3C24X0（smdk2410确实配置了这个选项），

然后根据是否定义了CONFIG_S3C2400（smdk2410没有配置这个选项）来确定pWTCON、INTMSK、CLKDIVN等寄存器的地址。

接下来关闭看门狗：

    ldr     r0, =pWTCON
    mov     r1, #0x0
    str     r1, [r0]

接着设置中断屏蔽寄存器的值为0xffffffff：

    mov    r1, #0xffffffff
    ldr    r0, =INTMSK
    str    r1, [r0]

接着配置副中断屏蔽寄存器的值为0x3ff(总共有11个有效位，所以0x3ff表示第11位未屏蔽）

# if defined(CONFIG_S3C2410)
    ldr    r1, =0x3ff
    ldr    r0, =INTSUBMSK
    str    r1, [r0]
# endif

然后对分频进行设置：

而CLKDIVN最低位为0(CLKDIVN[0])时表示PCLK与HCLK相同，为1表示PCLK等于HCLK的1/2。

而CLKDIVN次低两位（CLKDIVN[2:1])为0时表示HCLK等于FCLK，为1时表示HCLK等于FCLK的1/2.

    /* FCLK:HCLK:PCLK = :: */
    /* default FCLK is  MHz ! */
    ldr    r0, =CLKDIVN
    mov    r1, #
    str    r1, [r0]

因为没有定义CONFIG_SKIP_LOWLEVEL_INIT，所以接下来会跳转到cpu_init_crit：

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif

cpu_init_crit代码如下：

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
    /*
     * flush v4 I/D caches
     */
    mov    r0, #
    mcr    p15, , r0, c7, c7,     /* flush v3/v4 cache */
    mcr    p15, , r0, c8, c7,     /* flush v4 TLB */

    /*
     * disable MMU stuff and caches
     */
    mrc    p15, , r0, c1, c0,
    bic    r0, r0, #0x00002300    @ clear bits , : (--V- --RS)
    bic    r0, r0, #0x00000087    @ clear bits , : (B--- -CAM)
    orr    r0, r0, #0x00000002    @ set bit  (A) Align
    orr    r0, r0, #0x00001000    @ set bit  (I) I-Cache
    mcr    p15, , r0, c1, c0, 

    /*
     * before relocating, we have to setup RAM timing
     * because memory timing is board-dependend, you will
     * find a lowlevel_init.S in your board directory.
     */
    mov    ip, lr

    bl    lowlevel_init

    mov    lr, ip
    mov    pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

cpu_init_crit功能先flush Cache和TLB,然后禁止MMU和Cache,然后会跳转到lowlevel_init执行。

lowlevel_init位于board/samsung/smdk2410/lowlevel_init.S文件，代码如下：

_TEXT_BASE:
    .word    CONFIG_SYS_TEXT_BASE

.globl lowlevel_init
lowlevel_init:
    /* memory control configuration */
    /* make r0 relative the current location so that it */
    /* reads SMRDATA out of FLASH rather than memory ! */
    ldr     r0, =SMRDATA
    ldr    r1, _TEXT_BASE
    sub    r0, r0, r1
    ldr    r1, =BWSCON    /* Bus Width Status Controller */
    add     r2, r0, #*
:
    ldr     r3, [r0], #
    str     r3, [r1], #
    cmp     r2, r0
    bne     0b

    /* everything is fine now */
    mov    pc, lr

    .ltorg
/* the literal pools origin */

SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .word 0x32
    .word 0x30
    .word 0x30

lowlevel_init用于初始化SDRAM,对2410的bank0-bank7都进行初始化。寄存器含义可以查看http://www.embedu.org/Column/Column169.htm

接下来就是执行“bl _main”跳转到_main函数，这属于第二阶段初始化的内容，在下一篇博文中再进行讲述。

总之，第一阶段初始化内容如下：

（1）进入SVC32模式

（2）关闭看门狗，屏蔽中断

（3）设置分频（FCLK：HCLK：PCLK = 1：2：4）

（4）Flush Cache和TLB， 禁止MMU和Cache

（5）初始化SDRAM(即配置Bank0-Bank7)