FPGA学习过程（二）

项目：数码管动态显示时间

首先建立一个计时一秒的模块,作为数码管显示的需要

 module timer_s(
        input wire clk,
        input wire rst_n,
        output wire [31:0] timer
 );

 reg [25:0] cnt;
 reg [31:0] timer_num;
 parameter osc_frequency = 50_000_000;

 initial timer_num <= 0;

 always @(posedge clk or negedge rst_n)begin
        if(! rst_n)begin
            cnt <= 0;
            timer_num <= 0;
        end

        else begin
            if(cnt == osc_frequency -1)begin
                cnt <= 0;
                timer_num <= timer_num + 1;
            end
            else
                cnt <= cnt + 1;
        end
 end

 assign timer = timer_num;

 endmodule
 

接下来是数码管显示模块

module display_smg (
    input wire clk ,
    input wire rst_n ,
    input wire [31:0] timer,
    output wire [6:0] smg ,
    output wire [3:0] dig
);
reg [6:0] smg_reg;
reg [3:0] dig_reg;
reg [3:0] num;
reg [3:0] wei;
reg [25:0] cnt;

parameter delay = 50_000 * 3 -1;

initial begin

    wei <= 0;
    cnt <= 0;

end

always @(posedge clk or negedge rst_n)begin
    if(! rst_n)begin
        cnt <= 0;
        dig_reg <= 4'b1111;
    end

    else begin
        if(cnt == delay)begin
             cnt <= 0;
             wei = wei + 1;
             if(wei > 3) wei = 0;
             dig_reg <= 4'b1111;
             if(dig_reg[wei] == 1)
                dig_reg[wei] <= 0;

        end

        else
             cnt <= cnt + 1;

    end

end

always @(*)begin
    case (wei)
        0:    num <= timer % 10;
        1:    num <= timer /10 % 10;
        2:    num <= timer /100 % 10;
        3:    num <= timer /1000 % 10;
        default:num <= 0;
    endcase
end

always @(*)begin
        case (num)
                0:smg_reg <= 7'b0000001;
                1:smg_reg <= 7'b1001111;
                2:smg_reg <= 7'b0010010;
                3:smg_reg <= 7'b0000110;
                4:smg_reg <= 7'b1001100;
                5:smg_reg <= 7'b0100100;
                6:smg_reg <= 7'b0100000;
                7:smg_reg <= 7'b0001111;
                8:smg_reg <= 7'b0000000;
                9:smg_reg <= 7'b0000100;
                default:smg_reg <= 7'b0000001;
        endcase
end

assign smg = smg_reg;
assign dig = dig_reg;

endmodule

然后在顶层文件中将俩个模块相连就行了，总体感觉在开发fpga很轻松