uvm_reg_block——寄存器模型（七）

这是寄存器模型的顶层

//------------------------------------------------------------------------
// Class: uvm_reg_block
//
// Block abstraction base class
//
// A block represents a design hierarchy. It can contain registers,
// register files, memories and sub-blocks.
//
// A block has one or more address maps, each corresponding to a physical
// interface on the block.
//
//------------------------------------------------------------------------
virtual class uvm_reg_block extends uvm_object;

   local uvm_reg_block  parent;

   local static bit     m_roots[uvm_reg_block];
   local int unsigned   blks[uvm_reg_block];
   local int unsigned   regs[uvm_reg];
   local int unsigned   vregs[uvm_vreg];
   local int unsigned   mems[uvm_mem];
   local bit            maps[uvm_reg_map];

   // Variable: default_path
   // Default access path for the registers and memories in this block.
   uvm_path_e      default_path = UVM_DEFAULT_PATH;

   local string         default_hdl_path = "RTL";
   local uvm_reg_backdoor backdoor;
   local uvm_object_string_pool #(uvm_queue #(string)) hdl_paths_pool;
   local string         root_hdl_paths[string];

   local bit            locked;

   local int            has_cover;
   local int            cover_on;
   local string         fname;
   local int            lineno;

   local static int id;