verilog behaviral modeling -- procedural timing contronls

1.delay control : an expression specifies the time duration between initially encountering the statement and when the statement actually executes.

the delay expressiong can be dynamic function of the state of the circuit,but it can be a simple number that separates statement

executions in time.

2.event control: which allows statement execution to be delayed until the occurence of some simulation event occurring in a procedure executing

concurrently with this procedure.

a simulation event can be a change of value on a net or variable(an implicit event) or the occurrence of an explicity named event

that is triggered from other procedures(an explicit event).

most often , an event control is p positive or negative edge on a clock signal.

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Simulation time can advance by one of the following three methods:

1.a delay control   ----> introduced by the symbol #

2.an event control  -----> introduced by the symbol @

3.the wait statement ----> operates like a combination of the event control and the while loop

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Delay control:

1.the delay expression evaluates to an unknow or high-impedance value, it shall be interpreted as zero delay.

2.the delay expression evaluates to a negative value, it shall be interpreted as a two-complement unsigned integer of

the same size as a time variable.

3.specify parameters are permitted in the delay expression.

eg: #10 rega = regb;

#D   rega = regb;  //D is parameter

#((d+e)/2) rega = regb;

 #regr  regr = regr + 1;   // delay is the value in regr

Event control:

1.implicity event( a value change on a net or variable)

2.explicity  event(the occurrence of a declared event即named event)

1.a negedge : from 1 to x / z /0; from x /z to 0

2.a posedge : from x/z/0 to 1    ; from x /z to 1

1.an implicity event shall be detected on any change in the value of the expression.

2.an edge event shall be detected only on the least significant bit (LSB)of the expression.

3.a change of value in any operand of the expression without a change in the expression in the result of the                                                 expression shall not be detected as an event.

@xx statements;

@(posedge xx) statements;

@(negedge xx) statements;

an event shall not hold any data. The following are the characteristic of a named event:

---It can be made to occur at any particular time.

---It has no time duration

--- Its occurrence can be recognized by using the event control

事件event 可以做或运算：

@(trig or enable) rega = regb;

@(posedge clk_a or posedge clk_b or trig) rega = regb;

可以把上面的or换成逗号（，）。

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对@*解析：

All net and variable indentifiers that appear in the statement will be automatically added to the event expression with

these exception:

1.Identifiers that only appear in wait or event expressions

2.Identifiers that only appear as a hierachical_variable_identifier in the variable_lvalue of the left_hand side of assignments

Nets and variables that appear on the right_hand side of assignments,in function and task calls, in case and conditional                                          expressions, as an index variable on the left-hand side of assignments, or as variables in case item expressions shall all be                                     included by these rules.

eg1: //此例子或许可以实现event与操作

always@*  begin   ///equivalent to @(b)

@(i) kid = b;   //i is not added to @*

end

eg2:

always@*begin //same as @(a or en)

y = 8'bff;

y[a] = !en;

eg3:

always@* begin //same as @(a or en)

next = 4'b0;

case(1'b1)

state[IDLE] : if(go) next[READ] = 1'b1;

else    next[IDLE]  = 1'b1;

state[READ] :          next[DLY]   = 1'b1;

state[DLY]   : if(!ws) next[DONE]  = 1'b1;

else    next[READ]  = 1'b1;

state[DONE] :            next[IDLE]   = 1'b1;

endcase

end

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level-sensitive event control / edge-senstive event control

1.@(xx)

@(posedge xx)

@(negedge xx)

分别是双边沿、上升沿、下降沿三种事件控制格式。

2.wait(xx) 是电平事件控制 ,xx为真是执行wait后面的语句。

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intra-assignment timing controls / inter-assignment timing controls

1. An intra-assignment delay or event control shall delay the assignment of the new value to the left-hand side,but

right-hand expression shall be evaluated before the delay,instead of after the delay .

2. the intra-assignment delay and event control can be applied to both blocking assignments and nonblocking                                                         assignments.（此条Verilog标准讲的不是很细，有些模糊）

3.the number of occurrences of an event can be variable

repeat (a) @(event_expression)

INTRA-ASSIGNMENT TIMING CONTROL EQUIVALENCE(有些像非阻塞赋值)

with intra-assignment construct                                                                      without intra-assignment construct

a = #5 b;  ===========================================>  begin

temp =b;

# a = temp;

end

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a = @(posedge clk) b;                                                                                       begin

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 temp = b;

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　@(posedge clk);

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　a = temp;

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　end

----------------------------------------------------------------------------------------------------------------------------------------------------------

a = repeat(3) @(posedge clk) b;                                                                       begin

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　temp = b;

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　@(posedge clk);

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　@(posedge clk);

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　@(posedge clk);

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　a = temp;

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　end

PS:1.intra-assignment can prevent  a race-condition

fork            ///data swap

a = #4 b;

b = #4 a;

end

2.intra-assignment waiting for events is also effective

fork          ///data shift

a = @(posedge clk)  b;

b = @(posedge clk) c;

end