Wishbone接口通用RAM

 /*
 ************************************************************************************************
 *    File   : wb_ram.v
 *    Module : wb_ram
 *    Author : Lyu Yang
 *    Date   : 01,01,1970
 *    Description : wishbone generic ram
 ************************************************************************************************
 */

 // synthesis translate_off
 `timescale 1ns / 10ps
 // synthesis translate_on
 module wb_ram (
     input    wire                wb_clk_i,
     input    wire                wb_rst_i,
     input    wire                wb_cyc_i,
     input    wire                wb_stb_i,
     input    wire                wb_we_i,
     input    wire    [:]        wb_sel_i,
     input   wire    [:]        wb_adr_i,
     input    wire    [:]        wb_dat_i,
     output    reg        [:]      wb_dat_o,
     output    reg                 wb_ack_o
 );

 parameter mem_words = ;

 wire [:]        wr_data;

 // mux for data to ram
 assign wr_data[:] = wb_sel_i[] ? wb_dat_i[:] : wb_dat_o[:];
 assign wr_data[:] = wb_sel_i[] ? wb_dat_i[:] : wb_dat_o[:];
 assign wr_data[: ] = wb_sel_i[] ? wb_dat_i[: ] : wb_dat_o[: ];
 assign wr_data[ : ] = wb_sel_i[] ? wb_dat_i[ : ] : wb_dat_o[ : ];

 // genarate ack signal
 always @ (posedge wb_clk_i)
 begin
     if(wb_ack_o)
         wb_ack_o <= 'b0;
     else if(wb_cyc_i & wb_stb_i & !wb_ack_o)
         wb_ack_o <= 'b1;
     else wb_ack_o <= 'b0;
 end

 // memory
 reg [: ] ram [ : mem_words - ];

 initial $readmemh("../../data.txt", ram);

 always @ (posedge wb_clk_i)
 begin
     wb_dat_o <= ram[wb_adr_i[:]];
     if(wb_cyc_i & wb_stb_i & wb_we_i & wb_ack_o)
         ram[wb_adr_i[:]] <= wr_data;
 end 

 endmodule