CVO实现过程

 module vid_cvo #(
        parameter H_SYNC                 =  ,
        parameter H_FRONT_PORCH =  ,
        parameter H_BACK_PORCH  = ,
        parameter V_SYNC            =   ,
        parameter V_FRONT_PORCH =   ,
        parameter V_BACK_PORCH  =  

    )(
        input             clk,
        input             rst_p,
        input     [:] idata,
        input             ivalid,
        input             vid_sop,
        input             vid_eop,

//        input [5:0] h_sync_pixcels,
//        input [5:0] h_front_porch_pixcels,
//        input [5:0] h_back_porch_pixcels,
//        input [5:0] v_sync_lines,
//        input [5:0] v_front_porch_lines,
//        input [5:0] v_back_porch_lines,

        output reg din_ready,

        input [:] col,
        input [:] row,

        output reg[:] odata,
        output reg v_sync,
        output reg h_sync,
        output reg de

    );

    parameter S_H_SYNC = 'b00;
    parameter S_H_BACK_PORCH = 'b01;
    parameter S_H_ACTIVE   = 'b10;
    parameter S_H_FRONT_PORCH = 'b11;
    parameter S_V_SYNC = 'b00;
    parameter S_V_BACK_PORCH = 'b01;
    parameter S_V_ACTIVE   = 'b10;
    parameter S_V_FRONT_PORCH = 'b11;

    reg [:] h_pre_state = S_H_SYNC;
    reg [:] h_nx_state = S_H_SYNC;
    reg [:] v_pre_state = S_V_SYNC;
    reg [:] v_nx_state = S_V_SYNC;

    reg [:] h_cnt     = ;
    reg [:] v_cnt     = ;
    reg [:] sync_code = ;
    reg           de_r     = 'b0;
//    reg [15:0] data_r1 = 16'd0;
//    reg [15:0] data_r2 = 16'd0;
//    reg [15:0] data_r3 = 16'd0;
//    reg [15:0] data_r4 = 16'd0;
    wire             fifo_wr_en ;
    wire [:] fifo_wr_data;
    wire             fifo_almost_full;
    wire            fifo_almost_empty;
    wire [:] fifo_rd_data;
    reg            fifo_rd_en = 'b0;
    reg             vid_sop_r = 'b0;
    wire            pos_vid_sop;
    reg                fifo_rst_p = 'b1;
    reg                fifo_rd_valid = 'b0;
    reg [:] fifo_rd_data_r = 'd0;
    reg [:] sync_code_r = 'd0;
    reg [:] sync_code_r1 = 'd0;
    reg                  de_r1 = 'b0;
    reg                    de_r2 = 'b0;
    reg                    h_sync_r = 'b0;
    reg                    h_sync_r1 = 'b0;
    reg                    h_sync_r2 = 'b0;
    reg                    v_sync_r  = 'b0;
    reg                    v_sync_r1 = 'b0;
    reg                    v_sync_r2 = 'b0;

    always @( posedge clk )
    begin
        vid_sop_r <= vid_sop;
    end

    assign pos_vid_sop = {vid_sop_r,vid_sop} == 'b01;

    assign fifo_wr_en = (vid_sop | vid_eop ) ?'b0: ivalid ?1'b1 :'b0;
    assign fifo_wr_data = idata;

    always @( posedge clk )
    begin
        if( fifo_almost_empty )
                 din_ready<= 'b1;
        else if( fifo_almost_full )
                din_ready <= 'b0;
        else
                din_ready <= 'b0;
    end

    always @( posedge clk )
    begin
            if( rst_p )
                    fifo_rst_p <= 'b1;
            else if( pos_vid_sop )
                    fifo_rst_p <= 'b0;
            else
                    fifo_rst_p <= fifo_rst_p;
    end

    fifo_w18d512    fifo_w18d512_inst (
    .clock ( clk ),
    .data ( fifo_wr_data ),
    .rdreq ( fifo_rd_en ),
    .sclr ( fifo_rst_p ),
    .wrreq ( fifo_wr_en ),
    .almost_full ( fifo_almost_full ),
    .almost_empty( fifo_almost_empty),
    .empty (  ),
    .full (  ),
    .q ( fifo_rd_data ),
    .usedw (  )
    );
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    fifo_rd_en <= 'b1;
            else
                    fifo_rd_en <= 'b0;
    end

    always @( posedge clk )
    begin
            fifo_rd_valid <= fifo_rd_en;
    end

    always @( posedge clk )
    begin
            if( fifo_rd_valid )
                    fifo_rd_data_r <= fifo_rd_data;
            else
                    fifo_rd_data_r <= 'd0;
    end

/***********************************************************************

***********************************************************************/    

    always @( posedge clk )//or posedge rst_p
    begin
            if( fifo_rst_p ) begin
                h_pre_state <= S_H_SYNC;
                v_pre_state <= S_V_SYNC;

            end else begin
                h_pre_state <= h_nx_state;
                v_pre_state <= v_nx_state;
            end
    end

    always @( * )
    begin
            case( h_pre_state )
            S_H_SYNC :
                    if( h_cnt == H_SYNC - )
                            h_nx_state  <= S_H_BACK_PORCH;
                    else
                            h_nx_state <= S_H_SYNC;

            S_H_BACK_PORCH :
            begin
                    if( h_cnt == H_BACK_PORCH - )
                            h_nx_state  <= S_H_ACTIVE;
                    else
                            h_nx_state <= S_H_BACK_PORCH;
            end
            S_H_ACTIVE    :
            begin
                   if( h_cnt == col - )
                        h_nx_state  <= S_H_FRONT_PORCH;
                else
                        h_nx_state <= S_H_ACTIVE;        

            end
            S_H_FRONT_PORCH :
            begin
                if( h_cnt == H_FRONT_PORCH - )
                        h_nx_state  <= S_H_SYNC;
                else
                        h_nx_state <= S_H_FRONT_PORCH;          

            end
            default:;
            endcase    

    end

    always @( * )
    begin
            case( v_pre_state )
            S_V_SYNC :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                            if( v_cnt == V_SYNC - )
                                    v_nx_state = S_V_BACK_PORCH;
                            else
                                v_nx_state = S_V_SYNC;
                    end else begin
                            v_nx_state = S_V_SYNC;
                    end
            end
            S_V_BACK_PORCH :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                            if( v_cnt == V_BACK_PORCH - )
                                    v_nx_state = S_V_ACTIVE;
                            else
                                    v_nx_state = S_V_BACK_PORCH;
                    end else begin
                            v_nx_state = S_V_BACK_PORCH;
                    end
            end
            S_V_ACTIVE    :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                           if( v_cnt == row - )
                                v_nx_state = S_V_FRONT_PORCH;
                            else
                                    v_nx_state = S_V_ACTIVE;
                end else begin
                        v_nx_state = S_V_ACTIVE;
                end       

            end
            S_V_FRONT_PORCH :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                        if( v_cnt == V_FRONT_PORCH -'b1 )
                                v_nx_state = S_V_SYNC;
                            else
                                    v_nx_state = S_V_FRONT_PORCH;
                    end else begin
                            v_nx_state = S_V_FRONT_PORCH;
                    end
            end
            default:;
            endcase
//            end else begin
//                    v_nx_state = v_nx_state;
//            end
//
    end
/***********************************************************************
cnt
***********************************************************************/
    always @( posedge clk )
    begin
        if( fifo_rst_p ) begin
            h_cnt <= ;
        end else begin
            case( h_nx_state )
            S_H_SYNC :
            begin
                     if( h_pre_state == S_H_FRONT_PORCH  )  //&& h_cnt == H_FRONT_PORCH -1
                            h_cnt <= ;
                    else
                            h_cnt <= h_cnt + 'b1;
            end
            S_H_BACK_PORCH :
            begin
                    if( h_pre_state == S_H_SYNC )//&& h_cnt == H_SYNC -1)
                            h_cnt <= ;
                    else
                            h_cnt <= h_cnt + 'b1;
            end
            S_H_ACTIVE    :
            begin
                if( h_pre_state == S_H_BACK_PORCH)// && h_cnt == H_BACK_PORCH -1)
                        h_cnt <= ;
                else
                        h_cnt <= h_cnt + 'b1;
            end
            S_H_FRONT_PORCH :
            begin
                if( h_pre_state == S_H_ACTIVE )//&& h_cnt == col -1)
                        h_cnt <= ;
                else
                        h_cnt <= h_cnt + 'b1;
            end
            default:;
            endcase
    end
    end 

    always @( posedge clk or posedge fifo_rst_p )
    begin
        if( fifo_rst_p)
            v_cnt <= ;
        else  begin
            if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  )
            begin
                case( v_nx_state )
                S_V_SYNC :
                begin
                    if( v_pre_state == S_V_FRONT_PORCH )
                            v_cnt <= ;
                    else
                            v_cnt <= v_cnt + 'b1;
                end

                S_V_BACK_PORCH :
                begin
                    if( v_pre_state  ==  S_V_SYNC )
                            v_cnt <= ;
                    else
                            v_cnt <= v_cnt + 'b1;
                end
                S_V_ACTIVE    :
                begin
                   if( v_pre_state  ==  S_V_BACK_PORCH )
                        v_cnt <= ;
                else
                        v_cnt <= v_cnt + 'b1;        

                end
                S_V_FRONT_PORCH :
                begin
                if( v_pre_state  ==  S_V_ACTIVE )
                        v_cnt <= ;
                else
                        v_cnt <= v_cnt + 'b1;       

                end
                default:;
                endcase
            end
        end
    end

/***********************************************************************
h_sync v_sync de
***********************************************************************/
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_SYNC )
                    h_sync_r <= 'b1;
            else
                    h_sync_r <= 'b0;
    end

    always @( posedge clk )
    begin
            if( v_nx_state == S_V_SYNC )
                    v_sync_r <= 'b1;
            else
                    v_sync_r <= 'b0;
    end

    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    de_r <= 'b1;
            else
                    de_r <= 'b0;
    end
/***********************************************************************

***********************************************************************/    

    always @( posedge clk )
    begin
        if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                case( h_cnt )
                        H_BACK_PORCH - : sync_code <= 'habab;
                        H_BACK_PORCH - : sync_code <= 'h0000;
                        H_BACK_PORCH - : sync_code <= 'h0000;
                        H_BACK_PORCH - : sync_code <= 'hffff;
                default:sync_code <= 'd0;
                endcase
        else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 'hffff;
                else begin
                    case(h_cnt )
                         : sync_code <= 'h0000;
                         : sync_code <= 'h0000;
                         : sync_code <= 'hb6b6;
                    default:sync_code <= 'd0;
                    endcase
                end
        else if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_ACTIVE)) begin
            case(h_cnt )
                      H_BACK_PORCH - : sync_code <= 'h8080;
                      H_BACK_PORCH - : sync_code <= 'h0000;
                      H_BACK_PORCH - : sync_code <= 'h0000;
                      H_BACK_PORCH - : sync_code <= 'hffff;
              default:sync_code <= 'd0;
              endcase
        end
        else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_ACTIVE)) begin
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 'hffff;
                else begin
                    case(h_cnt )
                             : sync_code <= 'h0000;
                             : sync_code <= 'h0000;
                             : sync_code <= 'h9d9d;
                    default:sync_code <= 'd0;
                    endcase
                end
        end
        else begin
                    sync_code <= 'd0;
        end
    end
/***********************************************************************
sync
***********************************************************************/    

    always @( posedge clk )
    begin
        sync_code_r <= sync_code;
        sync_code_r1<= sync_code_r;
        de_r1 <= de_r;
        de_r2 <= de_r1;
        h_sync_r1 <= h_sync_r;
        h_sync_r2 <= h_sync_r1;
        v_sync_r1 <= v_sync_r;
        v_sync_r2 <= v_sync_r1;

    end
    always @( posedge clk )
    begin
            odata <= sync_code_r1 + fifo_rd_data_r;
            h_sync <= h_sync_r2;
            v_sync <= v_sync_r2;
            de     <= de_r2;
    end

    endmodule