Tcl之Read files for synthesis

　　The following file is to read all design files into syntehsis tool automatically, like Cadence RTL Compiler.

 set srcbasic          ${HDLPATH}/01_VHDLBasiclib
 set srcasictop        ${HDLPATH}/02_ASIC/01_Top
 set srcrfid           ${HDLPATH}/02_ASIC/02_RFID
 set srcmsp            ${HDLPATH}/02_ASIC/03_MSP430
 set srcperiph         ${HDLPATH}/02_ASIC/04_Periph
 set srcopenmsp        ${srcmsp}/openmsp430/core/rtl/verilog

 set_attribute hdl_search_path  "${srcmsp}/include"

 # filelists
 set fileListBasicLib  "
     ... ...
 $srcbasic/pkg_types.vhd
 $srcbasic/ffd.vhd
     ... ...
 "

 set fileListCommon "
     ... ...
 $srcasictop/pkg_infil.vhd
 $srcasictop/xfabmem_ent.vhd
     ... ...
 "

 set fileList15693 "
 $srcrfid/iso15693/pkg_iso15693cmd.vhd
 $srcrfid/iso15693/rx15693sym.vhd
     ... ...
 "
 set fileList14443  "
 $srcrfid/iso14443/pkg_iso14443cmd.vhd
 $srcrfid/iso14443/rx14443byte.vhd
     ... ...
 "

 set fileListRFID "
     ... ...
 $srcrfid/fifo.vhd
     ... ...
 "

 set fileListOpenMspXFAB "
 $srcmsp/omsp_and_gate.vhd
 $srcmsp/omsp_clock_gate.vhd
 "

 set fileListOpenMsp "
     ... ...
 $srcopenmsp/omsp_clock_mux.v
 $srcopenmsp/omsp_clock_module.v
     ... ...
 "

 set fileListPeriph "
 $srcmsp/gpio/msp_io.vhd
     ... ...
 "

 set fileListMsp "
     ... ...
 $srcmsp/msp430asic.vhd
 "

 set fileListTop "
     ... ...
 $srcasictop/infil.vhd
 "

 read_hdl -vhdl  ${fileListBasicLib}    -library  edclib
 read_hdl -vhdl  ${fileListCommon}
 read_hdl -vhdl  ${fileList15693}
 read_hdl -vhdl  ${fileList14443}
 read_hdl -vhdl  ${fileListRFID}
 read_hdl -vhdl  ${fileListOpenMspXFAB}
 read_hdl -v2001 ${fileListOpenMsp}
 read_hdl -vhdl  ${fileListPeriph}
 read_hdl -vhdl  ${fileListMsp}
 read_hdl -vhdl  ${fileListTop}