S32K148-SPI（裸机开发）

S32K148-SPI驱动开发步骤：

1）SPI引脚复用

2）enable PCC for  SPI

3）disable module

4）部分寄存器配置：控制寄存器，时钟寄存器，发送寄存器，接收寄存器

5）enable SPI

SPI初始化函数、：

void spi0_init(void)
{
    /*pin mux for spi0
    gpio_init(PTe, 6, 1, 1);//引脚初始化
    PORTE->PCR[2] |= (1<<9);
    PORTE->PCR[1] |= (1<<9);
    PORTE->PCR[0] |= (1<<9);
    /*Disable clocks to modify PCS ( default)*/
    PCC->PCCn[PCC_LPSPI0_INDEX] = 0;
    /*(default) Peripheral is present.
    * Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
    PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000;
    /*disable module for cfg*/
    LPSPI0->CR    = 0x00000000;
    LPSPI0->IER   = 0x00000000;
    LPSPI0->DER   = 0x00000000;
    LPSPI0->CFGR0 = 0x00000000;
    /* Configurations: master mode
         * PCSCFG=0: PCS[3:2] are enabled
         * OUTCFG=0: Output data retains last value when CS negated
         * PINCFG=0: SIN is input, SOUT is output
         * MATCFG=0: Match disabled
         * PCSPOL=0: PCS is active low
         * NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full
         * AUTOPCS=0: does not apply for master mode
         * SAMPLE=0: input data sampled on SCK edge
         * MASTER=1: Master mode*/
    LPSPI0->CFGR1 = 0x00000001;
    /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc
     * CPOL=1: SCK inactive state is low
     * CPHA=1: Change data on SCK lead'g, capture on trail'g edge
     * PRESCALE=2: Functional clock divided by 2**2 = 4,40M/4=10M
     * PCS=0: Transfer using PCS0
     * LSBF=0: Data is transfered MSB first
     * BYSW=0: Byte swap disabled
     * CONT, CONTC=0: Continuous transfer disabled
     * RXMSK=0: Normal transfer: rx data stored in rx FIFO
     * TXMSK=0: Normal transfer: data loaded from tx FIFO
     * WIDTH=0: Single bit transfer
     * FRAMESZ=7: # bits in frame = 7+1=8 */
    LPSPI0->TCR = 0xC8000007;
    /* Clock dividers based on prescaled func'l clk of 100 nsec
         * SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec)
         * PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec)
         * DBT=8: Delay between Transfers = 8+2 = 10 (1 usec)
         * SCKDIV=8: SCK divider =8+2 = 10 ,10M/10=1M(1 usec: 1 MHz baud rate) *///sck=18
    LPSPI0->CCR = 0x04040812;
    /* RXWATER=0: Rx flags set when Rx FIFO >0
     * TXWATER=3: Tx flags set when Tx FIFO <= 3  */
    LPSPI0->FCR = 0x00000003;
    /* Enable module for operation
         * DBGEN=1: module enabled in debug mode
         * DOZEN=0: module enabled in Doze mode
         * RST=0: Master logic not reset
         * MEN=1: Module is enabled  */
    LPSPI0->CR = 0x00000009;
}

SPI发送接收函数

uint8_t LPSPI0_TransmitReceice_1Byte (uint8_t senddata)
{
    uint8_t receivedata;
    /* Wait for Tx FIFO available */
    while((LPSPI0->SR & 0x1) == 0);
    /* Transmit data */
    LPSPI0->TDR = senddata;
    /* Wait at least one RxFIFO entry */
    while((LPSPI0->SR & 0x2) >> 1 == 0);//如果没有接收设备，处于死循环，影响程序执行
    /* Read received data */
    receivedata = LPSPI0->RDR;
    /* Clear TDF flag */
    LPSPI0->SR |= 0x1;
    /* Clear RDF flag  */
    LPSPI0->SR |= 0x2;
    return receivedata;
}