基于FPGA的VGA显示设计（二）
参照 CrazyBingo 的 基于FPGA的VGA可移植模块终极设计代码 的工程代码风格，模块化处理了上一篇的代码，并增加了一点其它图形。
顶层模块：
/****************************************************
* Module Name : VGA_color_all.v
* Author : yllinux 博客：http://www.cnblogs.com/yllinux/
* Target Device : Cyclone IV E ( EP4CE6F17C8 )
* Tool versions : Quartus II 12.1
* Create Date : 2017-7-29
* Revision : v1.0
* Description : 彩条显示模块化，并增加几种显示模式
*****************************************************/ module VGA_color_all
(
input clk,
input rst_n, output hs,
output vs,
output [:] rgb
); /*****************************************************
分辨率选择，取消注释的有效
******************************************************/
//`define resolution_1280_1024_60FPS_108MHz
//`define resolution_1024_768_60FPS_65MHz
`define resolution_1920_1080_60FPS_148MHz
//`define resolution_
//`define resolution_
//`define resolution_800_600_72FPS_50MHz
//`define resolution_640_480_60FPS_25MHz /****************************************************
参数配置，其中的 DELAY 项可调 [0, 31]
****************************************************/
`ifdef resolution_1280_1024_60FPS_108MHz
parameter
DELAY = 'd3, //模式切换延时
DUTY_CYCLE = , //PLL占空比
DIVIDE_DATA = , //PLL除
MULTIPLY_DATA = , //PLL乘
PIXEL_FREQUENCY = 'd108_000000, //像素时钟，1秒
H_DISP = 'd1280, //行显示 Hor Addr Time
H_FRONT = 'd48, //行同步前 H Front Porch
H_SYNC = 'd112, //行同步 Hor Sync Time
H_BACK = 'd248, //行同步后 H Back Porch
H_TOTAL = 'd1688, //行总计 Hor Total Time
V_DISP = 'd1024, //场 Ver Addr Time
V_FRONT = 'd1, // V Front Porch
V_SYNC = 'd3, // Ver Sync Time
V_BACK = 'd38, // V Back Porch
V_TOTAL = 'd1066; // Ver Total Time
`endif `ifdef resolution_800_600_72FPS_50MHz
parameter
DELAY = 'd3,
DUTY_CYCLE = ,
DIVIDE_DATA = ,
MULTIPLY_DATA = ,
PIXEL_FREQUENCY = 'd50_000000,
H_DISP = 'd800,
H_FRONT = 'd56,
H_SYNC = 'd120,
H_BACK = 'd64,
H_TOTAL = 'd1040,
V_DISP = 'd600,
V_FRONT = 'd37,
V_SYNC = 'd6,
V_BACK = 'd23,
V_TOTAL = 'd666;
`endif `ifdef resolution_640_480_60FPS_25MHz
parameter
DELAY = 'd3,
DUTY_CYCLE = ，
DIVIDE_DATA = ，
MULTIPLY_DATA = ，
PIXEL_FREQUENCY = 'd25_000000,
H_DISP = 'd640,
H_FRONT = 'd16,
H_SYNC = 'd96,
H_BACK = 'd48,
H_TOTAL = 'd800,
V_DISP = 'd480,
V_FRONT = 'd10,
V_SYNC = 'd2,
V_BACK = 'd33,
V_TOTAL = 'd525;
`endif `ifdef resolution_1024_768_60FPS_65MHz
parameter
DELAY = 'd3,
DUTY_CYCLE = ,
DIVIDE_DATA = ,
MULTIPLY_DATA = ,
PIXEL_FREQUENCY = 'd65_000000,
H_DISP = 'd1024,
H_FRONT = 'd24,
H_SYNC = 'd136,
H_BACK = 'd160,
H_TOTAL = 'd1344,
V_DISP = 'd768,
V_FRONT = 'd3,
V_SYNC = 'd6,
V_BACK = 'd29,
V_TOTAL = 'd806;
`endif `ifdef resolution_1920_1080_60FPS_148MHz
parameter
DELAY = 'd3,
DUTY_CYCLE = ,
DIVIDE_DATA = ,
MULTIPLY_DATA = ,
PIXEL_FREQUENCY = 'd1485_00000,
H_DISP = 'd1920,
H_FRONT = 'd88,
H_SYNC = 'd44,
H_BACK = 'd148,
H_TOTAL = 'd2200,
V_DISP = 'd1080,
V_FRONT = 'd4,
V_SYNC = 'd5,
V_BACK = 'd36,
V_TOTAL = 'd1125;
`endif `ifdef resolution
parameter
DELAY = 'd3,
DUTY_CYCLE =
DIVIDE_DATA =
MULTIPLY_DATA =
PIXEL_FREQUENCY = 'd
H_DISP = 'd
H_FRONT = 'd
H_SYNC = 'd
H_BACK = 'd
H_TOTAL = 'd
V_DISP = 'd
V_FRONT = 'd
V_SYNC = 'd
V_BACK = 'd
V_TOTAL = 'd
`endif /************************************************
clk_pll instantiation （PLL核实例化）
*************************************************/
wire clk_vga;
clk_pll //模块名
#(
.DUTY_CYCLE ( DUTY_CYCLE ),
.DIVIDE_DATA ( DIVIDE_DATA ),
.MULTIPLY_DATA ( MULTIPLY_DATA )
)
clk_pll_inst //实例化名
(
.inclk0 ( clk ),
.c0 ( clk_vga )
); /************************************************
display_vga instantiation （显示模块实例化）
*************************************************/
//wire [11:0] xpos_vga_driver;
//wire [11:0] ypos_vga_driver;
//wire [15:0] data_vga_driver;
wire [:] xpos_vga; //例化括号里代表连线的名称，上面注释的三条是错的
wire [:] ypos_vga;
wire [:] data_vga;
display_vga //模块名
#( //参数传递
.H_DISP ( H_DISP ),
.V_DISP ( V_DISP ),
.PIXEL_FREQUENCY ( PIXEL_FREQUENCY ),
.DELAY ( DELAY )
)
display_vga_inst //实例化名
(
.clk_vga_display ( clk_vga ),
.rst_n_display ( rst_n ),
.xpos_vga_display ( xpos_vga ),
.ypos_vga_display ( ypos_vga ), .data_vga_display ( data_vga )
); /************************************************
driver_vga instantiation （驱动模块实例化）
*************************************************/
driver_vga
#(
.H_DISP ( H_DISP ),
.H_FRONT ( H_FRONT ),
.H_SYNC ( H_SYNC ),
.H_BACK ( H_BACK ),
.H_TOTAL ( H_TOTAL ),
.V_DISP ( V_DISP ),
.V_FRONT ( V_FRONT ),
.V_SYNC ( V_SYNC ),
.V_BACK ( V_BACK ),
.V_TOTAL ( V_TOTAL )
)
driver_vga_inst
(
.clk_vga_driver ( clk_vga ),
.rst_n_driver ( rst_n ),
.data_vga_driver ( data_vga ), .rgb_vga_driver ( rgb ),
.hs_vga_driver ( hs ),
.vs_vga_driver ( vs ),
.xpos_vga_driver ( xpos_vga ),
.ypos_vga_driver ( ypos_vga )
); endmodule
驱动模块：
module driver_vga
#(
/***********************************************
1280 x 1024 @ 60 Hz
***********************************************/
parameter
H_DISP = 'd1280, //行显示 Hor Addr Time
H_FRONT = 'd48, //行同步前 H Front Porch
H_SYNC = 'd112, //行同步 Hor Sync Time
H_BACK = 'd248, //行同步后 H Back Porch
H_TOTAL = 'd1688, //行总计 Hor Total Time V_DISP = 'd1024, //场 Ver Addr Time
V_FRONT = 'd1, // V Front Porch
V_SYNC = 'd3, // Ver Sync Time
V_BACK = 'd38, // V Back Porch
V_TOTAL = 'd1066 // Ver Total Time
)
(
input clk_vga_driver, //VGA像素时钟
input rst_n_driver, //异步复位信号，低电平有效
input [:] data_vga_driver, //RGB565格式 output [:] rgb_vga_driver, //接收要显示的色彩
output reg hs_vga_driver, //VGA管脚 行同步
output reg vs_vga_driver, //VGA管脚 场同步
output [:] xpos_vga_driver, //像素横坐标位置
output [:] ypos_vga_driver //像素纵坐标位置
); /*****************************************************
驱动核心，行场同步信号发生器与同步
*****************************************************/
reg [:] hcnt; //定义行计数器
always @ (posedge clk_vga_driver or negedge rst_n_driver)
begin
if (!rst_n_driver)
hcnt <= 'd0;
else
begin
if (hcnt <= H_TOTAL - 'd1) //行计数取值区间【0, H_TOTAL - 1】
hcnt <= hcnt + 'd1;
else
hcnt <= 'd0;
end
end
always @ (posedge clk_vga_driver or negedge rst_n_driver)
begin
if (!rst_n_driver)
hs_vga_driver <= 'b0;
else
begin
// 像素点区间【H_DISP + H_FRONT, H_DISP +H_FRONT + H_SYNC -1】
if (hcnt >= H_DISP + H_FRONT - 'd1 && hcnt < H_DISP +H_FRONT + H_SYNC - 12'd1)
hs_vga_driver <= 'b1;
else
hs_vga_driver <= 'b0;
end
end reg [:] vcnt;
always @ (posedge clk_vga_driver or negedge rst_n_driver)
begin
if (!rst_n_driver)
vcnt <= 'd0;
else
begin
if (hcnt == H_DISP - 'd1)
begin
if (vcnt < V_TOTAL - 'd1)
vcnt <= vcnt + 'd1;
else
vcnt <= 'd0;
end
else
vcnt <= vcnt;
end
end
always @ (posedge clk_vga_driver or negedge rst_n_driver)
begin
if (!rst_n_driver)
vs_vga_driver <= 'b0;
else
begin
if (vcnt >= V_DISP + V_FRONT - 'd1 && vcnt < V_DISP + V_FRONT + V_SYNC - 12'd1)
vs_vga_driver <= 'b1;
else
vs_vga_driver <= 'b0;
end
end /************************************************************
输出横竖坐标和有效区域数据
************************************************************/
assign xpos_vga_driver = (hcnt < H_DISP) ? hcnt : 'd0; //把显示期的行计数值赋给横坐标变量
assign ypos_vga_driver = (vcnt < V_DISP) ? vcnt : 'd0; //把显示期的场计数值赋给纵坐标变量
assign rgb_vga_driver = (hcnt < H_DISP && vcnt < H_DISP) ? data_vga_driver : 'd0; //显示期进行图像输出 endmodule
显示模块：
module display_vga
#(
/***********************************************
1280 x 1024 @ 60 Hz
***********************************************/
parameter
H_DISP = 'd1280,
V_DISP = 'd1024,
PIXEL_FREQUENCY = 'd108_000000,
DELAY = 'd3
)
(
input clk_vga_display,
input rst_n_display,
input [:] xpos_vga_display, //输入横坐标
input [:] ypos_vga_display, //输入纵坐标 output reg [:] data_vga_display //输出产生的图像数据
); /****************************************************************
定义本地参数颜色，RGB565
****************************************************************/
localparam
RED = 'hF800, //11111_000000_00000 红
GREEN = 'h07E0, //00000_111111_00000 绿
BLUE = 'h001F, //00000_000000_11111 蓝
WHITE = 'hFFFF, //11111_111111_11111 白
BLACK = 'h0000, //00000_000000_00000 黑
YELLOW = 'hFFE0, //11111_111111_00000 黄
MAGENTA= 'hF81F, //11111_000000_11111 紫（品红、洋红）
CYAN = 'h07FF; //00000_111111_11111 青（蓝绿） /****************************************************************
延时，产生模式选择信号
****************************************************************/
reg [:] cnt_display; //在像素频率下计数，计满为1秒
reg [:] mod_display; //显示模式
reg [:] delay_display; //延时，秒为单位，最多31秒
always @ (posedge clk_vga_display or negedge rst_n_display)
begin
if (!rst_n_display)
begin
cnt_display <= 'd0;
mod_display <= 'd0;
end
else
begin
if (cnt_display < PIXEL_FREQUENCY) //判断是否计到1秒
begin
cnt_display <= cnt_display + 'd1;
end
else
begin
cnt_display <= 'd0;
if (delay_display < DELAY) //延时 DELAY 秒
delay_display <= delay_display + 'd1;
else
begin
delay_display <= 'd0;
if (mod_display < 'd7) //模式选择
mod_display <= mod_display + 'd1;
else
mod_display <= 'd0;
end
end
end
end /*************************************************************
方格1 小
*************************************************************/
reg [:] grid1_data_display;
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
grid1_data_display <= BLACK;
else
if (xpos_vga_display[] == ^ ypos_vga_display[] == )
grid1_data_display <= WHITE;
else
grid1_data_display <= BLACK; /*************************************************************
方格2 大
*************************************************************/
reg [:] grid2_data_display;
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
grid2_data_display <= BLACK;
else
if (xpos_vga_display[] == ^ ypos_vga_display[] == )
grid2_data_display <= WHITE;
else
grid2_data_display <= BLACK; /*************************************************************
彩条1 横
*************************************************************/
reg [:] color_bar1_display;
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
color_bar1_display <= BLACK;
else
begin
if (ypos_vga_display >= && ypos_vga_display < (V_DISP >> ))
color_bar1_display <= RED;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= GREEN;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= BLUE;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= WHITE;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= BLACK;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= YELLOW;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= MAGENTA;
else if (ypos_vga_display >= (V_DISP >> )* && ypos_vga_display < (V_DISP >> )*)
color_bar1_display <= CYAN;
else
color_bar1_display <= BLACK;
end /*************************************************************
彩条2 竖
*************************************************************/
reg [:] color_bar2_display;
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
color_bar2_display <= BLACK;
else
begin
if (xpos_vga_display >= && xpos_vga_display < (H_DISP >> ))
color_bar2_display <= RED;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= GREEN;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= BLUE;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= WHITE;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= BLACK;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= YELLOW;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= MAGENTA;
else if (xpos_vga_display >= (H_DISP >> )* && xpos_vga_display < (H_DISP >> )*)
color_bar2_display <= CYAN;
else
color_bar2_display <= BLACK;
end /*************************************************************
花型矩阵
**************************************************************/
reg [:] flower_matrix_display;
wire [:] flower_result = xpos_vga_display * ypos_vga_display;
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
flower_matrix_display <= BLACK;
else
flower_matrix_display <= flower_result[:]; /*************************************************************
选择显示模式
*************************************************************/
always @ (posedge clk_vga_display or negedge rst_n_display)
if (!rst_n_display)
data_vga_display <= 'd0;
else
case (mod_display)
'd0 : data_vga_display <= grid1_data_display;
'd1 : data_vga_display <= grid2_data_display;
'd2 : data_vga_display <= color_bar1_display;
'd3 : data_vga_display <= color_bar2_display;
'd4 : data_vga_display <= RED;
'd5 : data_vga_display <= GREEN;
'd6 : data_vga_display <= BLUE;
'd7 : data_vga_display <= flower_matrix_display;
default : data_vga_display <= BLACK;
endcase endmodule
PLL 模块：
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll // ============================================================
// File Name: clk_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************ //Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details. // synopsys translate_off
`timescale ps / ps
// synopsys translate_on
module clk_pll #(
parameter //提取参数，方便例化时参数传递
DUTY_CYCLE = ,
DIVIDE_DATA = ,
MULTIPLY_DATA =
)
(
inclk0,
c0
); input inclk0;
output c0; wire [:] sub_wire0;
wire [:] sub_wire4 = 'h0;
wire [:] sub_wire1 = sub_wire0[:];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [:] sub_wire3 = {sub_wire4, sub_wire2}; altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset ('b0),
.clkbad (),
.clkena ({{'b1}}),
.clkloss (),
.clkswitch ('b0),
.configupdate ('b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({{'b1}}),
.fbin ('b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena ('b1),
.phasecounterselect ({{'b1}}),
.phasedone (),
.phasestep ('b1),
.phaseupdown ('b1),
.pllena ('b1),
.scanaclr ('b0),
.scanclk ('b0),
.scanclkena ('b1),
.scandata ('b0),
.scandataout (),
.scandone (),
.scanread ('b0),
.scanwrite ('b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = DIVIDE_DATA,
altpll_component.clk0_duty_cycle = DUTY_CYCLE,
altpll_component.clk0_multiply_by = MULTIPLY_DATA,
altpll_component.clk0_phase_shift = "",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = ,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = ; endmodule // ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
Testbench：
`timescale ns/ ps
module VGA_color_all_tb();
reg clk;
reg rst_n;
// wires
wire hs;
wire [:] rgb;
wire vs; // assign statements (if any)
VGA_color_all i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.hs(hs),
.rgb(rgb),
.rst_n(rst_n),
.vs(vs)
);
initial
begin
clk = ;
rst_n = ;
# rst_n = ;
# rst_n = ;
end
always
begin
# clk = ~clk;
end
endmodule
仿真波形：
RTL 图：
实测图：
引脚分配（仅适用于Cyclone IV E -- EP4CE6F17C8）：
以下为每隔三秒显示的图形：
如有错误还请指出，如有侵权还请告知，如需转载请注明出处！
本人博客：http://www.cnblogs.com/yllinux/
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