VHDL之std_logic_1164

This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.

1　　std_logic_1164

 PACKAGE std_logic_1164 IS

  3     -------------------------------------------------------------------
  4     -- logic state system  (unresolved)
  5     -------------------------------------------------------------------
     TYPE std_ulogic IS ( 'U',  -- Uninitialized
                          'X',  -- Forcing  Unknown
                          '',  -- Forcing
                          '',  -- Forcing
                          'Z',  -- High Impedance
                          'W',  -- Weak     Unknown
                          'L',  -- Weak
                          'H',  -- Weak
                          '-'   -- Don't care
                        );
 16     --------------------------------------------------------------------------
 17     -- unconstrained array of std_ulogic for use with the resolution function
 18     --------------------------------------------------------------------------
     TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;

 21     -------------------------------------------------------------------
 22     -- resolution function
 23     -------------------------------------------------------------------
     FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;

 26     -------------------------------------------------------------------
 27     -- *** industry standard logic type ***
 28     -------------------------------------------------------------------
     SUBTYPE std_logic IS resolved std_ulogic;

 31     -----------------------------------------------------------------------
 32     -- unconstrained array of std_logic for use in declaring signal arrays
 33     -----------------------------------------------------------------------
     TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

 36     -----------------------------------------------------------------------------
 37     -- common subtypes
 38     -----------------------------------------------------------------------------
     SUBTYPE X01     IS resolved std_ulogic RANGE 'X' TO ''; -- ('X','','')
     SUBTYPE X01Z    IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','','','Z')
     SUBTYPE UX01    IS resolved std_ulogic RANGE 'U' TO ''; -- ('U','X','','')
     SUBTYPE UX01Z   IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','','','Z') 

 44     -------------------------------------------------------------------
 45     -- overloaded logical operators
 46     -------------------------------------------------------------------    

     FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
     FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
     FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
     FUNCTION "nor"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
     FUNCTION "xor"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
     function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
     FUNCTION "not"  ( l : std_ulogic                 ) RETURN UX01;

 56     -----------------------------------------------------------------------
 57     -- vectorized overloaded logical operators
 58     -----------------------------------------------------------------------
     FUNCTION "and"  ( l, r : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "and"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

     FUNCTION "nand" ( l, r : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

     FUNCTION "or"   ( l, r : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "or"   ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

     FUNCTION "nor"  ( l, r : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "nor"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

     FUNCTION "xor"  ( l, r : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "xor"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

 74 --  -----------------------------------------------------------------------
 75 --  Note : The declaration and implementation of the "xnor" function is
 76 --  specifically commented until at which time the VHDL language has been
 77 --  officially adopted as containing such a function. At such a point,
 78 --  the following comments may be removed along with this notice without
 79 --  further "official" ballotting of this std_logic_1164 package. It is
 80 --  the intent of this effort to provide such a function once it becomes
 81 --  available in the VHDL standard.
 82 --  -----------------------------------------------------------------------
     function "xnor" ( l, r : std_logic_vector  ) return std_logic_vector;
     function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

     FUNCTION "not"  ( l : std_logic_vector  ) RETURN std_logic_vector;
     FUNCTION "not"  ( l : std_ulogic_vector ) RETURN std_ulogic_vector;

 89     -------------------------------------------------------------------
 90     -- conversion functions
 91     -------------------------------------------------------------------
     FUNCTION To_bit       ( s : std_ulogic;        xmap : BIT := '')
                           RETURN BIT;
     FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '')
                           RETURN BIT_VECTOR;
     FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '')
                           RETURN BIT_VECTOR;

     FUNCTION To_StdULogic      (b : BIT              ) RETURN std_ulogic;
     FUNCTION To_StdLogicVector (b : BIT_VECTOR       ) RETURN std_logic_vector;
     FUNCTION To_StdLogicVector (s : std_ulogic_vector) RETURN std_logic_vector;
     FUNCTION To_StdULogicVector(b : BIT_VECTOR      ) RETURN std_ulogic_vector;
     FUNCTION To_StdULogicVector(s : std_logic_vector) RETURN std_ulogic_vector;

105     -------------------------------------------------------------------
106     -- strength strippers and type convertors
107     -------------------------------------------------------------------    

     FUNCTION To_X01  ( s : std_logic_vector  ) RETURN  std_logic_vector;
     FUNCTION To_X01  ( s : std_ulogic_vector ) RETURN  std_ulogic_vector;
     FUNCTION To_X01  ( s : std_ulogic        ) RETURN  X01;
     FUNCTION To_X01  ( b : BIT_VECTOR        ) RETURN  std_logic_vector;
     FUNCTION To_X01  ( b : BIT_VECTOR        ) RETURN  std_ulogic_vector;
     FUNCTION To_X01  ( b : BIT               ) RETURN  X01;       

     FUNCTION To_X01Z ( s : std_logic_vector  ) RETURN  std_logic_vector;
     FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN  std_ulogic_vector;
     FUNCTION To_X01Z ( s : std_ulogic        ) RETURN  X01Z;
     FUNCTION To_X01Z ( b : BIT_VECTOR        ) RETURN  std_logic_vector;
     FUNCTION To_X01Z ( b : BIT_VECTOR        ) RETURN  std_ulogic_vector;
     FUNCTION To_X01Z ( b : BIT               ) RETURN  X01Z;      

     FUNCTION To_UX01  ( s : std_logic_vector  ) RETURN  std_logic_vector;
     FUNCTION To_UX01  ( s : std_ulogic_vector ) RETURN  std_ulogic_vector;
     FUNCTION To_UX01  ( s : std_ulogic        ) RETURN  UX01;
     FUNCTION To_UX01  ( b : BIT_VECTOR        ) RETURN  std_logic_vector;
     FUNCTION To_UX01  ( b : BIT_VECTOR        ) RETURN  std_ulogic_vector;
     FUNCTION To_UX01  ( b : BIT               ) RETURN  UX01;       

130     -------------------------------------------------------------------
131     -- edge detection
132     -------------------------------------------------------------------
     FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN;
     FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;

136     -------------------------------------------------------------------
137     -- object contains an unknown
138     -------------------------------------------------------------------
     FUNCTION Is_X ( s : std_ulogic_vector ) RETURN  BOOLEAN;
     FUNCTION Is_X ( s : std_logic_vector  ) RETURN  BOOLEAN;
     FUNCTION Is_X ( s : std_ulogic        ) RETURN  BOOLEAN;

 END std_logic_1164;

2　　resolution function　　

     function resolved ( s : std_ulogic_vector ) return std_ulogic;
         variable result : std_ulogic := 'Z';  -- weakest state default
     begin
 4         -- the test for a single driver is essential otherwise the
 5         -- loop would return 'X' for a single driver of '-' and that
 6         -- would conflict with the value of a single driver unresolved signal.
         if  s'length = 1 then
             return s(s'low);
         else
             for i in s'range loop
                 result := resolution_table(result, s(i));
             end loop;
         end if;
         return result;
     end resolved;

     constant resolution_table : stdlogic_table := (
20     --      ---------------------------------------------------------
21     --      |  U    X    0    1    Z    W    L    H    -        |   |
22     --      ---------------------------------------------------------
             ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
             ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
             ( 'U', 'X', '', 'X', '', '', '', '', 'X' ), -- | 0 |
             ( 'U', 'X', 'X', '', '', '', '', '', 'X' ), -- | 1 |
             ( 'U', 'X', '', '', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
             ( 'U', 'X', '', '', 'W', 'W', 'W', 'W', 'X' ), -- | W |
             ( 'U', 'X', '', '', 'L', 'W', 'L', 'W', 'X' ), -- | L |
             ( 'U', 'X', '', '', 'H', 'W', 'W', 'H', 'X' ), -- | H |
             ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )  -- | - |
         );