Counter 1000

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q
);

题目网站

 1 module top_module (
 2     input clk,
 3     input reset,
 4     output OneHertz,
 5     output [2:0] c_enable
 6 ); //
 7 wire[3:0]    one, ten, hundred;
 8     assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};
 9
10     assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);
11
12     bcdcount counter0 (clk, reset, c_enable[0], one);
13     bcdcount counter1 (clk, reset, c_enable[1], ten);
14     bcdcount counter2 (clk, reset, c_enable[2], hundred);
15
16     //bcdcount counter0 (clk, reset, c_enable[0]/*, ... */);
17     //bcdcount counter1 (clk, reset, c_enable[1]/*, ... */);
18
19 endmodule

再写：

1. assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};的理解。
   
   答：首先要理解c_enable的作用，可以理解为这个计数器的小时、分钟、秒，这三个部分，每一个部分想启动一次计数，都要有这部分对应的enable来作为使能信号。联系现实生活的时间计数（只不过这里是10倍10倍的计数，而不是60），秒的部分自然是每个周期都要运作，分钟的部分要在第10个周期，也即one == 4'd9，小时的部分要在第100个周期，也即one == 4'd9 && ten == 4'd9，因为调用的是bcd计数器，记不到100，只能10x10的来计数。
2. assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);的理解。
   
   答：实现了“从 1000 Hz 时钟中，导出一个 1 Hz 信号，称为 OneHertz”的功能。