STEP模块——电子钟

原理

显示时分秒（日期也可以加上），两个按键调节时间

原理图

代码

 /*--------------------------------------------------------------------------------------
 -- Filename ﹕ debounce_module.v
 -- Author ﹕tony-ning
 -- Description ﹕按键消抖
 -- Called by ﹕Top module
 -- Revision History ﹕15-10-16
 -- Revision 1.0
 -- Company ﹕
 -- Copyright(c)  All right reserved
 ---------------------------------------------------------------------------------------*/

 module debounce_module
 (
     CLK, //采集时钟，40Hz
     RSTn, //系统复位信号
     BUTTON_IN, //按键输入信号
     BUTTON_OUT //消抖后的输出信号
 );
     input CLK;
     input RSTn;
     input BUTTON_IN;
     output BUTTON_OUT;

     reg key_reg1,key_reg2,key_out;
     reg [:]count2;

     always @( posedge CLK)//CLK 50M
         begin
         count2<=count2+;
         if(count2==)
         begin
             key_reg1<=BUTTON_IN;
             count2<=;
         end
         key_reg2<=key_reg1;
         key_out<=key_reg2&(!key_reg1);
      end

     assign BUTTON_OUT = key_out;

 endmodule

 /*     reg [23:0]cnt;//分频计数器
     reg CLK40HZ;//分频时钟
     reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;

     always@(posedge CLK ) //时钟分频
     begin
         if(!RSTn)
             cnt<=0;
         else if(cnt==24'd312_499)   //产生40Hz时钟脉冲
                 begin
                 cnt<=0;
                 CLK40HZ<=~CLK40HZ;//40hz时钟输出
                 end
             else begin
                 cnt<=cnt+1;
                 end
     end

     always @(posedge CLK40HZ or negedge RSTn)
     begin
         if(~RSTn)
             begin
             BUTTON_IN_Q <= 1'b1;
             BUTTON_IN_2Q <= 1'b1;
             BUTTON_IN_3Q <= 1'b1;
             end
         else
             begin
             BUTTON_IN_Q <= BUTTON_IN;
             BUTTON_IN_2Q <= BUTTON_IN_Q;
             BUTTON_IN_3Q <= BUTTON_IN_2Q;
             end
     end

     wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
 endmodule */

 /*
 module debounce_module
 (
     CLK, RSTn, KEY_set,KEY_add,Pin_set, Pin_add
 );

      input CLK;
      input RSTn;
      input KEY_set;
      input KEY_add;
      output Pin_set;
      output Pin_add;

      reg p=1'b0;//按键状态
      reg [23:0]cntt;
      reg k1f1,k1f2;//KEY_set上升沿检测
      reg k2f1,k2f2;//KEY_add上升沿检测

      parameter s_wait=1'b0;//等待按键状态
      parameter s_delay=1'b1;//按下延时状态

      assign Pin_set=k1f2&!k1f1;//读取按键下降沿
      assign Pin_add=k2f2&!k2f1;

      always @ ( posedge CLK or negedge RSTn )//按键消抖状态机
          if( !RSTn )
               begin
                   cntt <= 24'd0;
                   p <= s_wait;
                 end
         else case(p)
             s_wait: begin
                         k1f1<=KEY_set;//记录按键值
                         k1f2<=k1f1;

                         k2f1<=KEY_add;
                         k2f2<=k2f1;

                         if(Pin_set| Pin_add)//当按下，切换到延时并按键只输出一个时钟脉冲
                         begin
                             p<=s_delay;
                             k1f1<=0;
                             k1f2<=0;

                             k2f1<=0;
                             k2f2<=0;
                         end
                     end
             s_delay:if(cntt==24'd249_999)   //延时T=10ms
                         begin
                         cntt<=0;
                         p<=s_wait;
                         end
                     else begin
                         cntt<=cntt+1;
                         end

             endcase

 endmodule */

按键消抖

 /*--------------------------------------------------------------------------------------
 -- Filename ﹕ timer.v
 -- Author ﹕tony-ning
 -- Description ﹕timer-based STEP PGGA board
 -- Called by ﹕--
 -- Revision History ﹕15-10-26
 -- Revision 1.0
 --
 ---------------------------------------------------------------------------------------*/
 module timer
 (
     CLK,RSTn,keyset,keyadd,hour1,hour2,min1,min2,sec1,sec2,kstate,CLK2HZ
 );

     input CLK;
     input RSTn;
     input keyset;
     input keyadd;
     output reg[:]hour1;
     output reg[:]hour2;
     output reg[:]min1;
     output reg[:]min2;
     output reg[:]sec1;
     output reg[:]sec2;
     output [:]kstate;
     output reg CLK2HZ;
 /*-------------------------------define  --------------------------------------*/
     parameter idle='d0;//状态值定义
     parameter s_hour='d1;
     parameter s_minute='d2;
     parameter s_second='d3;

     reg [:]cnt;//分频计数器
     reg CLK1HZ;//分频时钟
     reg s_hour_cnt;//小时计数进位状态

     reg[:] p;  //状态机定义
     //reg[2:0] p_back; //状态返回

     assign kstate=p;

     always@(posedge CLK ) //时钟分频
     begin
         if(!RSTn)
             cnt<=;
         else if(cnt=='d24_999_999)   //产生1Hz时钟脉冲
                 begin
                 cnt<=;
                 CLK1HZ<=;
                 CLK2HZ<=~CLK2HZ;//2hz时钟输出
                 //min1<=0;
                 end
             else begin
                 cnt<=cnt+;
                 CLK1HZ<=;
                 //min1<=min1+1;
                 end
     end

     always@(posedge CLK )//状态机切换
     begin
         if(!RSTn)
         p<=idle;
         else
         case (p)
         idle: begin
                     if (keyset)
                     p<=s_hour;  //next设置小时
                     else p<=idle;
                     /***************************************/
                     case(s_hour_cnt)//小时计数
                     :    begin
                         if(hour1==)//10进位情况
                             begin
                             s_hour_cnt<=;
                             end
                         if(hour2 ==)
                             begin
                             hour2<=;
                             hour1<=hour1+;
                             end
                         //else hour2<=hour2+1;
                         end
                     :    if(hour2==)
                             begin
                             s_hour_cnt<=;//4进位情况
                             hour1<=;
                             hour2<=;
                             end
                     endcase
                     /***************************************/
                     if(min1==)        //分钟计数
                         begin
                         min1<=;
                         hour2<=hour2+;
                         end
                     else if(min2==)
                         begin
                         min1<=min1+;
                         min2<=;
                         end

                     /***************************************/
                     if(sec1==)        //秒计数
                         begin
                         sec1<=;
                         min2<=min2+;
                         end
                     else if(sec2==)
                         begin
                         sec1<=sec1+;
                         sec2<=;
                         end
                     else if(CLK1HZ)//每秒加一
                         sec2<=sec2+;
             end
         s_hour:
             begin
                    if (keyset)
                    p<=s_minute;  //next设置分钟
                    else p<=s_hour;
                    /***************************************/
                    if(keyadd)    //小时数值按键设定
                    begin
                         case(s_hour_cnt)//小时计数
                         :    begin
                             if(hour1==)//10进位情况
                                 begin
                                 s_hour_cnt<=;
                                 end
                             if(hour2 ==)
                                 begin
                                 hour2<=;
                                 hour1<=hour1+;
                                 end
                             else hour2<=hour2+;
                             end
                         :    if(hour2==)
                                 begin
                                 s_hour_cnt<=;//4进位情况
                                 hour1<=;
                                 hour2<=;
                                 end
                             else hour2<=hour2+;
                         endcase
                    end
             end
         s_minute:
             begin
                    if (keyset)
                    p<=s_second;  //next设置秒
                    else p<=s_minute;

                    if(keyadd)    //分钟数值按键设定
                    begin
                        if(min1== && min2==)        //分钟计数
                             begin
                             min1<=;
                             min2<=;
                             hour2<=hour2+;
                             end
                         else if(min2==)
                             begin
                             min1<=min1+;
                             min2<=;
                             end
                         else min2<=min2+;
                    end
             end
         s_second:begin
                        if (keyset)
                        p<=idle;  //next返回正常显示
                        else p<=s_second;

                        if(keyadd)    //秒数值按键设定
                        begin
                             if(sec1== && sec2==)        //秒计数
                                 begin
                                 sec1<=;
                                 min2<=min2+;
                                 end
                             else if(sec2==)
                                 begin
                                 sec1<=sec1+;
                                 sec2<=;
                                 end
                             else sec2<=sec2+;
                        end
                 end

         endcase
     end 

 endmodule
     

时间产生

 /*--------------------------------------------------------------------------------------
 -- Filename show_ctrl.v
 -- Author ﹕tony-ning
 -- Description ﹕数码管显示字符
 -- Called by ﹕Top module
 -- Revision History 5-10-16
 -- Revision 1.0
 -- Company
 -- Copyright(c)  All right reserved
 ---------------------------------------------------------------------------------------*/
 module show_ctrl
 (
     CLK,RSTn,hour1,hour2,min1,min2,sec1,sec2,kstate,CLK2HZ,lamp4,lamp3,lamp2,lamp1,dualpoint
 );

     input CLK,RSTn;
     input [:]hour1;
     input [:]hour2;
     input [:]min1;
     input [:]min2;
     input [:]sec1;
     input [:]sec2;
     input [:]kstate;
     input CLK2HZ;
     output reg[:]lamp4;
     output reg[:]lamp3;
     output reg[:]lamp2;
     output reg[:]lamp1;

     output reg dualpoint;

     /////////////////////////////////////////////////
     parameter idle='d0;
     parameter s_hour='d1;
     parameter s_minute='d2;
     parameter s_second='d3;

     parameter light='b0;
     parameter dark='b1;

     reg [:]number[:];

     ///////////////////////////////////////////////
     initial
     begin
     number[] ='b0000001;    //abcdefg    0
     number[] ='b1001111;    //abcdefg    1
     number[] ='b0010010;    //abcdefg    2
     number[] ='b0000110;    //abcdefg    3
     number[] ='b1001100;    //abcdefg    4
     number[] ='b0100100;    //abcdefg    5
     number[] ='b0100000;    //abcdefg    6
     number[] ='b0001111;    //abcdefg    7
     number[] ='b0000000;    //abcdefg    8
     number[] ='b0000100;    //abcdefg    9
     number[]='b1111111;    //abcdefg    null
     end

     always@(*)
     begin
     case(kstate)
     idle:         begin
                     lamp4<=number[hour1];
                     lamp3<=number[hour2];
                     if(CLK2HZ) dualpoint<=light;
                     else dualpoint<=dark;
                     lamp2<=number[min1];
                     lamp1<=number[min2];
                 end
     s_hour:     begin 

                     if(CLK2HZ)
                         begin
                         lamp4<=number[hour1];
                         lamp3<=number[hour2];
                         end
                     else
                         begin
                         lamp4<=number[];
                         lamp3<=number[];
                         end
                     dualpoint<=light;
                     lamp2<=number[min1];
                     lamp1<=number[min2];
                 end
     s_minute:     begin
                     lamp4<=number[hour1];
                     lamp3<=number[hour2];
                     dualpoint<=light;

                     if(CLK2HZ)
                         begin
                         lamp2<=number[min1];
                         lamp1<=number[min2];
                         end
                     else
                         begin
                         lamp2<=number[];
                         lamp1<=number[];
                         end
                 end
     s_second:     begin
                     lamp4<=number[];
                     lamp3<=number[];
                     dualpoint<=light;

                     if(CLK2HZ)
                         begin
                         lamp2<=number[sec1];
                         lamp1<=number[sec2];
                         end
                     else
                         begin
                         lamp2<=number[];
                         lamp1<=number[];
                         end

                 end
     endcase
     end

 endmodule

显示控制

 /*--------------------------------------------------------------------------------------
 -- Filename ﹕ top.v
 -- Author ﹕tony-ning
 -- Description ﹕top
 -- Called by ﹕
 -- Revision History ﹕15-10-16
 -- Revision 1.0
 -- Company ﹕
 -- Copyright(c)  All right reserved
 ---------------------------------------------------------------------------------------*/
 module top
 (
     CLK,RSTn,KEY_set,KEY_add,lamp4,lamp3,lamp2,lamp1,dualpoint
 );

     input CLK;
     input RSTn;
     input KEY_set;
     input KEY_add;
     output [:]lamp4;//数码管
     output [:]lamp3;
     output [:]lamp2;
     output [:]lamp1;
     output dualpoint;

     wire [:]hour1;
     wire [:]hour2;
     wire [:]min1;
     wire [:]min2;
     wire [:]sec1;
     wire [:]sec2;
     wire [:]kstate;
     wire CLK2HZ;
     wire Pin_set;
     wire Pin_add;

     debounce_module KEYset_debounce
     (
         .CLK(CLK),
         .RSTn(RSTn),
         .BUTTON_IN(KEY_set),
         .BUTTON_OUT(Pin_set)
     );

     debounce_module KEYadd_debounce
     (
         .CLK(CLK),
         .RSTn(RSTn),
         .BUTTON_IN(KEY_add),
         .BUTTON_OUT(Pin_add)
     );

     timer    time_generater
     (
         .CLK(CLK),
         .RSTn(RSTn),
         .keyset(Pin_set),
         .keyadd(Pin_add),
         .hour1(hour1),
         .hour2(hour2),
         .min1(min1),
         .min2(min2),
         .sec1(sec1),
         .sec2(sec2),
         .kstate(kstate),
         .CLK2HZ(CLK2HZ)
     );

     show_ctrl    show_module
     (
         .CLK(CLK),
         .RSTn(RSTn),
         .hour1(hour1),
         .hour2(hour2),
         .min1(min1),
         .min2(min2),
         .sec1(sec1),
         .sec2(sec2),
         .kstate(kstate),
         .CLK2HZ(CLK2HZ),
         .lamp4(lamp4),
         .lamp3(lamp3),
         .lamp2(lamp2),
         .lamp1(lamp1),
         .dualpoint(dualpoint)
     );

 endmodule
     

顶层调用

PCB

实物图