mig_7series_v4_0_data_gen_chk

mig_7series_v4_0_data_gen_chk

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2018/07/17 09:57:04
// Design Name:
// Module Name: mig_7series_v4_0_data_gen_chk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module mig_7series_v4_0_data_gen_chk # (

    parameter C_AXI_DATA_WIDTH     =  // Width of the AXI write and read data

    )
(

    input            clk,
    input            data_en,
    input  [:]  data_pattern,
    input            pattern_init,
    input  [:] prbs_seed_i,
    input         wrd_cntr_rst,
    input         rdata_vld,
    input [C_AXI_DATA_WIDTH-:]   rdata,
    input [C_AXI_DATA_WIDTH/-:] rdata_bvld,

    output reg [:] data_o,           // generated data
    output reg [:]  wrd_cntr        // Word count output

);

//---------------------------------------------------------------

    // 产生数据
    reg [:] lfsr_q = 'h0;
    always @(posedge clk)
    begin
        if(pattern_init)
        begin
            lfsr_q <= {prbs_seed_i + 'h55555555};
        end

        else if(data_en)
        begin
            lfsr_q[:] <= lfsr_q[:];
            lfsr_q[]    <= lfsr_q[] ^ lfsr_q[];
            lfsr_q[]    <= lfsr_q[] ^ lfsr_q[];
            lfsr_q[:]  <= lfsr_q[:];
            lfsr_q[]    <= lfsr_q[] ^ lfsr_q[];
              lfsr_q[]    <= lfsr_q[] ;
              lfsr_q[]    <= lfsr_q[];
        end
    end

//---------------------------------------------------------------

    // 数据向左移
      reg [:] walk0 = 'h0;
    always @(posedge clk)
    begin
        if(pattern_init)
            walk0 <= 'hFFFF_FFFE;

        else if(data_en)
            walk0 <= {walk0[:],walk0[]};
    end

//---------------------------------------------------------------

    //数据向左移
      reg [:] walk1 = 'h0;
      always @(posedge clk)
      begin
        if (pattern_init)
              walk1 <= 'h0000_0001;

        else if (data_en)
             walk1 <= {walk1[:],walk1[]};
    end

//---------------------------------------------------------------

    reg [:] prbs;
    always @(*)
    begin
        prbs = lfsr_q[:];
      end

//---------------------------------------------------------------

    // 选择输出数据的模式
    always @(*)
    begin
        case (data_pattern)
          'b001: data_o = prbs; // PRBS pattern
          'b010: data_o = walk0; // Walking zeros
          'b011: data_o = walk1; // Walking ones
          'b100: data_o = 32'hFFFF_FFFF; // All ones
          'b101: data_o = 32'h0000_0000; // All zeros
          default: data_o = 'h5A5A_A5A5;
        endcase
      end

//---------------------------------------------------------------

    //数据计数器
    always @(posedge clk)
    begin
          if (wrd_cntr_rst)
            wrd_cntr <= 'h00;

        else if (rdata_vld)
            wrd_cntr <= wrd_cntr + 'h01;
    end

//---------------------------------------------------------------

//此段代码是对输出的数据与读进来数据进行对比，如果不一致，则会产生错误标志位

    reg [C_AXI_DATA_WIDTH/-:]   msmatch_err_sig;

    genvar i;
    generate
        begin: data_check
            for(i = ; i <= (C_AXI_DATA_WIDTH/-); i=i+)
            begin:gen_data_check
                always @(posedge clk)
                    if(wrd_cntr_rst)
                        msmatch_err_sig[i] <= 'b0;
                    else if( rdata_vld &
                            (    (rdata[((i*)+):i*] != data_o[:] & rdata_bvld[(i*)]) |
                            (rdata[((i*)+):((i*)+)] != data_o[:] & rdata_bvld[(i*)+]) |
                            (rdata[((i*)+):((i*)+)] != data_o[:] & rdata_bvld[(i*)+]) |
                            (rdata[((i*)+):((i*)+)] != data_o[:] & rdata_bvld[(i*)+])  )
                        )
                        msmatch_err_sig[i] <= 'b1;
                    else
                        msmatch_err_sig[i] <= 'b0;

            end
        end

    endgenerate

    assign msmatch_err = |msmatch_err_sig;

endmodule

/*
add_force {/mig_7series_v4_0_data_gen_chk/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/mig_7series_v4_0_data_gen_chk/pattern_init} -radix hex {0 0ns} {1 200ns} {0 300ns}
add_force {/mig_7series_v4_0_data_gen_chk/prbs_seed_i} -radix hex {00000001 0ns}
add_force {/mig_7series_v4_0_data_gen_chk/data_en} -radix hex {0 0ns} {1 500ns} {0 600ns} {1 800ns} {0 900ns}

*/