SciTech-Hardware-SoC/FPGA-ASIC 设计 之 System C: 使用SystemC做 系统建模(硬件+软件) 以及 RTL和C/C++ 的联合仿真验证

SystemC: The language for System-level design, modeling and verification.

SystemC addresses the need for a system design and verification language that,

spans hardware and software. It is a language built in standard C++ by extending the language with the use of class libraries

https://news.eda365.com/tech/pcbsj/120011621071262.html

• 什么是 ASIC 设计
  
  ASIC 设计是开发复杂电子系统的过程。该系统可制造成特殊用途的半导体设备，通常用于大批量应用或具有严格的功耗、性能和尺寸限制的应用。
  
  ASIC 系统设计人员使用高级语言并通过仿真和可视化来开发和评估算法。

• 在半导体领域，开发产品 是抽象开发 规范的模型，通常用C/C++来实现。
  
  这里，SystemC和C++库提供了很大帮助。它简化了共存的硬件和软件设计的概念化。
  
  再加上实现TLM(事务级模型)间接口连接的TLM传送库，SystemC加速了整个验证过程。
  
  另一个重要方面是对所有不同的抽象架构, SystemC有增强的可移植性, 因此同一配置可以无缝地用于不同抽象级的设计。
  
  　TLM(事务级模型)是一种 对数字系统进行建模 的方案:
  
  - 将 模块之间的具体通信 与 功能单元或通信架构的具体实现 分开;
  
  - 把 总线或FIFO这类通信机制 模型化成Channel(信道)，用SystemC接口类将这些信道 提供给 模块和部件;
  
  - 这些 信道模型的信令接口功能 将取代 事务请求，这将掩藏具体的深层信息交换。

• 利用基于SystemC/TLM的方法学进行IP开发和FPGA建模, 发布时间：2022-03-11, 标签:总线
  
  随着系统级芯片技术的出现，设计规模越来越大，变得非常复杂，同时上市时间也大幅加速。
  
  因此, 正驱使 设计师开发新的方法学，用于复杂IP(硬件和软件)以及复杂系统的验证, 取代通常用的RTL方法学。
  
  ST公司建立了一个设计流，它从抽象开始，易于将模型写入IP的精密周期或RTL模型中。
  
  当转入低级抽象时，建模变得复杂，故IP验证也复杂。我们的方案适合于这种应用场景，
  
  因为它允许人们在各地相似的环境运行相同的测试平台和测试场景，
  
  因而允许在整个开发周期里高效地复用所有的测试范例和环境。

  示例目标是设计和实现UWB MAC(媒体访问层)IP。决定用SystemC来实现整个IP。
  
  还开发了抽象级具有不同程度变化的不同架构。所付出的努力比较少，得到的仿真速度很快，
  
  软件的实际编写也可以在设计周期非常早的阶段开始。
  
  该IP的RTL结果被移植到了SPEAr系列的FPGA。
  
  除ARM内核和相应的一系列IP，SPEAr还提供一个可配置逻辑块，这为用户在实现其逻辑功能时提供了无与伦比的灵活性。
  
  从而缩短了上市时间，同样也实现了空前的成本节省。

　　设计开发方法学

SystemC是用标准C/C++语言实现, 因此

• 即可以 描述硬件的: 系统设计、建模、仿真、测试、验证，

• 也可用 实现软件的: 系统软件、SDK、Library、...; 因为有C/C++的特性。

• https://www.cl.cam.ac.uk/teaching/0809/SysOnChip/additional/lg2-systemc/SystemC-Tutorial.pdf

• https://systemc.org/overview/systemc/

• https://www.doulos.com/

• http://www.forteds.com/:
  
  https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html
  
  Stratus High-Level Synthesis:
  
  - Cuts IP development from months to weeks
  
  - Enabling a Faster Path to Verified, High-Quality RTL(Register Transfer Level) Implementations from Abstract SystemC, C, or C++ Models

https://learnsystemc.com/codegen, Your data privacy:

• the auto-generation script runs 100% on the client side, your json contend stays locally, it is NOT uploaded to our server.
• The output SystemC code and text-based UML diagrams are temporary variables only visible locally. They don't exist anywhere in the internet.
  
  Nobody other than you can see those files.
• We use PlantUML's server to generate the UML diagrams.
  
  Thus, if you choose to see the diagrams, the wsd files will be submitted to plantuml, and the figures are returned.
  
  If this is concerning to you, you can opt-out the diagram generation, and launch plantuml manually to convert the wsd files into diagrams.

https://learnsystemc.com/basic/concurrency

SystemC Environment:

SystemC Methodology:

SystemC

The language for System-level design, modeling and verification

SystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with the use of class libraries. The language is particularly suited to model system's partitioning, to evaluate and verify the assignment of blocks to either hardware or software implementations, and to architect and measure the interactions between and among functional blocks. Leading companies in the intellectual property (IP), electronic design automation (EDA), semiconductor, electronic systems, and embedded software industries currently use SystemC for architectural exploration, to deliver high-performance hardware blocks at various levels of abstraction and to develop virtual platforms for hardware/software co-design. SystemC has been standardized by the Open SystemC Initiative (OSCI) and Accellera Systems Initiative and ratified as IEEE Std 1666-2023.

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Why SystemC?

An SoC is literally a system on a chip, consisting of both silicon and embedded software. Its design involves complex algorithm and architecture development and analysis similar to that performed in system design – a trade-off process that determines critical metrics, such as SOC performance, functionality, and power consumption.

Consequently, design tools must deliver orders-of-magnitude improvement in productivity at both architectural and implementation (RT and physical) levels. Moreover, tools must support a methodology that enables the early development of embedded application and system software, long before the availability of the RTL design or silicon prototype. Failure to achieve the requisite improvements in design productivity would result in missed market windows, and exploding design costs.

SystemC is a single, unified design and verification language that expresses architectural and other system-level attributes in the form of open-source C++ classes. It enables design and verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verification with RTL design. This higher level of abstraction enables considerably faster, more productive architectural trade-off analysis, design, and redesign than is possible at the more detailed RT level. Furthermore, verification of system architecture and other system-level attributes is orders of magnitude faster than that at the pin-accurate, timing-accurate RT level.

The SystemC community consists of a large and growing number of system design companies, semiconductor companies, intellectual property providers, and EDA tool vendors who have joined together to support and promote the standard.

SystemC Transaction Level Modeling (TLM)

The Transaction Level Modeling standard defines interfaces for SystemC, providing an essential framework for model exchange within companies and across the IP supply chain for architecture analysis, software development and performance analysis, and hardware verification. It explicitly addresses virtual prototyping in which SystemC models can easily be exchanged and arranged within a system, enabling the optimal reuse of models and modeling effort across different use cases.

More information about SystemC TLM

SystemC Analog/Mixed-Signal (AMS)

The SystemC AMS standard defined in IEEE Std 1666.1-2016 introduces system-level design and modeling of embedded Analog/Mixed-Signal (AMS) systems. SystemC AMS provides unique capabilities for the design and modeling of embedded analog/mixed-signal applications at higher levels of design abstraction. The SystemC AMS extensions define a uniform and standardized modeling approach that can be used in combination with digitally-oriented ESL design methods, supporting a design refinement methodology for functional modeling, architecture exploration, and virtual prototyping of embedded analog/mixed-signal systems.

More information about SystemC AMS

SystemC Configuration, Control and Inspection (CCI)

The goal of Configuration, Control and Inspection (CCI) is to improve efficiency and return-on-investment for model creators and tool providers. The CCI standards will allow suppliers to instrument models so that a rich user experience is enabled, and they will allow industry tools to leverage this instrumentation to provide powerful debug and analysis capabilities. The CCI working group has released the CCI 1.0 reference implementation to enable model configuration between SystemC models and tools.

More information about SystemC CCI

SystemC Synthesis Subset Standard

The SystemC Synthesis Subset Standard defines the syntactic elements in C++ and SystemC that are appropriate for use in SystemC models intended as input for High Level Synthesis (HLS) tools. The current version of the synthesizable subset is based on ISO/IEC 14882:2003 and IEEE Std 1666-2011, and the SystemC Synthesis Working Group is now looking to incorporate changes and enhancements that result from the evolution towards C++17 and IEEE Std 1666-2023.

More information about the SystemC Synthesis Subset Language Reference Manual

SystemC Verification (UVM-SystemC, SCV)

The UVM-SystemC library provides an implementation of the Universal Verification Methodology (UVM) in SystemC. The UVM-SystemC class library enables the development of scalable and reusable verification collateral for system-level verification and testing.

The SystemC Verification (SCV) library provides a common set of APIs that are used as a basis to verification activities with SystemC (generation of values under constraints, transaction recording, etc.). These APIs are implemented in all major SystemC simulators available on the market.

More information about SystemC Verification

Resources

Download SystemC/TLM standard, IEEE 1666-2023

Download SystemC AMS extensions standard, IEEE 1666.1-2016

SystemC Synthesis Subset Language Reference Manual, version 1.4.7

SystemC/TLM reference implementation on GitHub

SystemC Standards Update, December 2023