uvm - dut

module dut(clk,
           rst_n,
           rxd,
           rx_dv,
           txd,
           tx_en);
input clk;
input rst_n;
input[:] rxd;
input rx_dv;
output [:] txd;
output tx_en;

reg[:] txd;
reg tx_en;

always @(posedge clk) begin
   if(!rst_n) begin
      txd <= 'b0;
      tx_en <= 'b0;
   end
   else begin
      txd <= rxd;
      tx_en <= rx_dv;
   end
end
endmodule