Wishbone接口Altera JTAG UART

　　某些时候，我们在使用Altera FPGA的时候，尤其是涉及SoC系统的时候，通常需要一个串口与PC交互。使用Altera的USB-Blaster免去了外接一个串口。我们可以使用下面所述的IP核通过USB-Blaster将PC的字符传入FPGA或者从FPGA将字符数据发送至PC。

 alt_jtag_atlantic jtag_uart_alt_jtag_atlantic
 (
     .clk (clk),
     .r_dat (r_dat),
     .r_ena (r_ena),
     .r_val (r_val),
     .rst_n (rst_n),
     .t_dat (t_dat),
     .t_dav (t_dav),
     .t_ena (t_ena),
     .t_pause (t_pause)
      );

     defparam jtag_uart_alt_jtag_atlantic.INSTANCE_ID = ,
          jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = ,
          jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = ,
          jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";

　　下面贴出一个Wishbone接口的JTAG UART的代码描述：

 // synthesis translate_off
 `timescale 1ns / 1ps
 // synthesis translate_on

 module wb_jtag_uart (
     input           clk_i,
     input            rst_i,

     input            wb_stb_i,
     input            wb_cyc_i,
     output          wb_ack_o,
     input            wb_adr_i,
     input            wb_we_i,
     input   [:]     wb_dat_i,
     output  [:]    wb_dat_o,
     output            wb_irq_o
 );

 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */

 reg              ac;
 wire             activity;
 wire             av_irq;
 wire    [ : ] av_readdata;
 wire    [ : ] av_writedata;
 reg              av_waitrequest;
 reg              fifo_AE;
 reg              fifo_AF;
 wire             fifo_EF;
 wire             fifo_FF;
 wire             fifo_clear;
 wire             fifo_rd;
 wire    [  : ] fifo_rdata;
 wire    [  : ] fifo_wdata;
 reg              fifo_wr;
 reg              ien_AE;
 reg              ien_AF;
 wire             ipen_AE;
 wire             ipen_AF;
 reg              pause_irq;
 wire    [  : ] r_dat;
 wire             r_ena;
 reg              r_val;
 wire             rd_wfifo;
 reg              read_0;
 wire             rfifo_full;
 wire    [  : ] rfifo_used;
 reg              rvalid;
 reg              sim_r_ena;
 reg              sim_t_dat;
 reg              sim_t_ena;
 reg              sim_t_pause;
 wire    [  : ] t_dat;
 reg              t_dav;
 wire             t_ena;
 wire             t_pause;
 wire             wfifo_empty;
 wire    [  : ] wfifo_used;
 reg              woverflow;
 wire             wr_rfifo;
 wire             clk;
 wire             rst_n;
 wire             av_read_n;
 wire             av_write_n;
 wire             av_address;
 wire             av_chipselect;

 assign    clk = clk_i;
 assign     rst_n = ~rst_i;
 assign    av_address =  wb_adr_i;
 assign    wb_dat_o = av_readdata;
 assign    av_writedata = wb_dat_i;
 assign    wb_irq_o = av_irq;
 assign    wb_ack_o = ~av_waitrequest;
 assign    av_read_n = ~(wb_cyc_i & wb_stb_i & (~wb_we_i));
 assign    av_write_n = ~(wb_cyc_i & wb_stb_i & wb_we_i);
 assign    av_chipselect = wb_cyc_i & wb_stb_i;

 //avalon_jtag_slave, which is an e_avalon_slave
 assign rd_wfifo = r_ena & ~wfifo_empty;
 assign wr_rfifo = t_ena & ~rfifo_full;
 assign fifo_clear = ~rst_n;
 wb_jtag_uart_scfifo_w jtag_uart_scfifo_w
 (
   .clk         (clk),
   .fifo_FF     (fifo_FF),
   .fifo_clear  (fifo_clear),
   .fifo_wdata  (fifo_wdata),
   .fifo_wr     (fifo_wr),
   .r_dat       (r_dat),
   .rd_wfifo    (rd_wfifo),
   .wfifo_empty (wfifo_empty),
   .wfifo_used  (wfifo_used)
 );

 wb_jtag_uart_scfifo_r jtag_uart_scfifo_r
 (
   .clk        (clk),
   .fifo_EF    (fifo_EF),
   .fifo_clear (fifo_clear),
   .fifo_rd    (fifo_rd),
   .fifo_rdata (fifo_rdata),
   .rfifo_full (rfifo_full),
   .rfifo_used (rfifo_used),
   .rst_n      (rst_n),
   .t_dat      (t_dat),
   .wr_rfifo   (wr_rfifo)
 );

 assign ipen_AE = ien_AE & fifo_AE;
 assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
 assign av_irq = ipen_AE | ipen_AF;
 assign activity = t_pause | t_ena;
 always @(posedge clk or negedge rst_n)
 begin
   if (rst_n == )
       pause_irq <= 'b0;
   else // only if fifo is not empty...
   if (t_pause & ~fifo_EF)
       pause_irq <= 'b1;
   else if (read_0)
       pause_irq <= 'b0;
 end

 always @(posedge clk or negedge rst_n)
 begin
   if (rst_n == )
     begin
       r_val <= 'b0;
       t_dav <= 'b1;
     end
   else
     begin
       r_val <= r_ena & ~wfifo_empty;
       t_dav <= ~rfifo_full;
     end
 end

 always @(posedge clk or negedge rst_n)
 begin
   if (rst_n == )
     begin
       fifo_AE <= 'b0;
       fifo_AF <= 'b0;
       fifo_wr <= 'b0;
       rvalid <= 'b0;
       read_0 <= 'b0;
       ien_AE <= 'b0;
       ien_AF <= 'b0;
       ac <= 'b0;
       woverflow <= 'b0;
       av_waitrequest <= 'b1;
     end
   else
     begin
       fifo_AE <= {fifo_FF,wfifo_used} <= ;
       fifo_AF <= ('h40 - {rfifo_full,rfifo_used}) <= 8;
       fifo_wr <= 'b0;
       read_0 <= 'b0;
       av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
       if (activity)
           ac <= 'b1;
       // write
       if (av_chipselect & ~av_write_n & av_waitrequest)
           // addr 1 is control; addr 0 is data
           if (av_address)
             begin
               ien_AF <= av_writedata[];
               ien_AE <= av_writedata[];
               if (av_writedata[] & ~activity)
                   ac <= 'b0;
             end
           else
             begin
               fifo_wr <= ~fifo_FF;
               woverflow <= fifo_FF;
             end
       // read
       if (av_chipselect & ~av_read_n & av_waitrequest)
         begin
           // addr 1 is interrupt; addr 0 is data
           if (~av_address)
               rvalid <= ~fifo_EF;
           read_0 <= ~av_address;
         end
     end
 end

 assign fifo_wdata = av_writedata[ : ];
 assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 'b0;
 assign av_readdata = read_0 ? { {{'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {{'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };

 //synthesis read_comments_as_HDL on
 //  alt_jtag_atlantic jtag_uart_alt_jtag_atlantic
 //    (
 //      .clk (clk),
 //      .r_dat (r_dat),
 //      .r_ena (r_ena),
 //      .r_val (r_val),
 //      .rst_n (rst_n),
 //      .t_dat (t_dat),
 //      .t_dav (t_dav),
 //      .t_ena (t_ena),
 //      .t_pause (t_pause)
 //    );
 //
 //  defparam jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
 //           jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
 //           jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
 //           jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
 //
 //
 //synthesis read_comments_as_HDL off

 endmodule

 module wb_jtag_uart_scfifo_w (
                                      // inputs:
                                       clk,
                                       fifo_clear,
                                       fifo_wdata,
                                       fifo_wr,
                                       rd_wfifo,

                                      // outputs:
                                       fifo_FF,
                                       r_dat,
                                       wfifo_empty,
                                       wfifo_used
                                    );

 output           fifo_FF;
 output  [  : ] r_dat;
 output           wfifo_empty;
 output  [  : ] wfifo_used;
 input            clk;
 input            fifo_clear;
 input   [  : ] fifo_wdata;
 input            fifo_wr;
 input            rd_wfifo;

 wire             fifo_FF;
 wire    [  : ] r_dat;
 wire             wfifo_empty;
 wire    [  : ] wfifo_used;

 //synthesis read_comments_as_HDL on
 //  scfifo wfifo
 //    (
 //      .aclr (fifo_clear),
 //      .clock (clk),
 //      .data (fifo_wdata),
 //      .empty (wfifo_empty),
 //      .full (fifo_FF),
 //      .q (r_dat),
 //      .rdreq (rd_wfifo),
 //      .usedw (wfifo_used),
 //      .wrreq (fifo_wr)
 //    );
 //
 //  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
 //           wfifo.lpm_numwords = 64,
 //           wfifo.lpm_showahead = "OFF",
 //           wfifo.lpm_type = "scfifo",
 //           wfifo.lpm_width = 8,
 //           wfifo.lpm_widthu = 6,
 //           wfifo.overflow_checking = "OFF",
 //           wfifo.underflow_checking = "OFF",
 //           wfifo.use_eab = "ON";
 //
 //synthesis read_comments_as_HDL off

 endmodule

 module wb_jtag_uart_scfifo_r (
                                      // inputs:
                                       clk,
                                       fifo_clear,
                                       fifo_rd,
                                       rst_n,
                                       t_dat,
                                       wr_rfifo,

                                      // outputs:
                                       fifo_EF,
                                       fifo_rdata,
                                       rfifo_full,
                                       rfifo_used
                                    );
 output           fifo_EF;
 output  [  : ] fifo_rdata;
 output           rfifo_full;
 output  [  : ] rfifo_used;
 input            clk;
 input            fifo_clear;
 input            fifo_rd;
 input            rst_n;
 input   [  : ] t_dat;
 input            wr_rfifo;

 wire             fifo_EF;
 wire    [  : ] fifo_rdata;
 wire             rfifo_full;
 wire    [  : ] rfifo_used;

 //synthesis read_comments_as_HDL on
 //  scfifo rfifo
 //    (
 //      .aclr (fifo_clear),
 //      .clock (clk),
 //      .data (t_dat),
 //      .empty (fifo_EF),
 //      .full (rfifo_full),
 //      .q (fifo_rdata),
 //      .rdreq (fifo_rd),
 //      .usedw (rfifo_used),
 //      .wrreq (wr_rfifo)
 //    );
 //
 //  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
 //           rfifo.lpm_numwords = 64,
 //           rfifo.lpm_showahead = "OFF",
 //           rfifo.lpm_type = "scfifo",
 //           rfifo.lpm_width = 8,
 //           rfifo.lpm_widthu = 6,
 //           rfifo.overflow_checking = "OFF",
 //           rfifo.underflow_checking = "OFF",
 //           rfifo.use_eab = "ON";
 //
 //synthesis read_comments_as_HDL off

 endmodule

　　关于这个IP核（alt_jtag_atlantic）的寄存器的说明，在Altera的文档中有所说明。其实非常简单，只有两个32位的寄存器。