1080P60视频源---verilog

1080P60视频源---verilog

 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 // Company:
 // Engineer: chensimin
 //
 // Create Date: 2019/03/15 10:09:21
 // Design Name:
 // Module Name: video_source
 // Project Name:
 // Target Devices:
 // Tool Versions:
 // Description:
 //
 // Dependencies:
 //
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
 //
 //////////////////////////////////////////////////////////////////////////////////

  module video_source (

     input  wire      clk,
     input  wire      rest,
     output reg [:] video_y = 'h3FF,
     output reg [:] video_c = 'h3FF,
     output wire      data_enable,
     output reg       sync_h = ,
     output reg       sync_v = 

     );

 //---------------------------------------------------------------------------------------------------------------

 reg [:] h_count = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         h_count <= 'd2199;
     else if(h_count == 'd2199)
         h_count <= 'd0;
     else
         h_count <= h_count + 'd1;
 end

 //---------------------------------------------------------------------------------------------------------------

 reg  h_end   = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         h_end <= 'b0;
     else if(h_count == 'd2198)
         h_end <= 'b1;
     else
         h_end <= 'b0;
 end

 //---------------------------------------------------------------------------------------------------------------

 reg [:] v_count = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         v_count <= 'd1;
     else if(v_count == 'd1125 & h_count == 12'd2199)
         v_count <= 'd1;
     else if(h_end)
         v_count <= v_count + 'd1;
 end

 //---------------------------------------------------------------------------------------------------------------

 wire b0, b1, b2, b3, b4, b5, b6, b7;
 wire [:] condition_b;

 assign b0 = v_count >= 'd1     & v_count < 12'd41     ;
 assign b1 = v_count == 'd41    & h_count <= 12'd2198  ;
 assign b2 = v_count >= 'd42    & v_count < 12'd1121   ;
 assign b3 = v_count == 'd1121  & h_count <= 12'd2198  ;
 assign b4 = v_count == 'd1121  & h_count == 12'd2199  ;
 assign b5 = v_count >= 'd1122  & v_count < 12'd1125   ;
 assign b6 = v_count == 'd1125  & h_count <= 12'd2198  ;
 assign b7 = v_count == 'd1125  & h_count == 12'd2199  ;

 assign condition_b = {b0, b1, b2, b3, b4, b5, b6, b7};

 //---------------------------------------------------------------------------------------------------------------

 reg v = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         v <= 'b0;
     else
     begin
         case(condition_b)
             'b1000_0000:
                 v <= 'b1;
             'b0100_0000:
                 v <= 'b1;
             'b0010_0000:
                 v <= 'b0;
             'b0001_0000:
                 v <= 'b0;
             'b0000_1000:
                 v <= 'b1;
             'b0000_0100:
                 v <= 'b1;
             'b0000_0010:
                 v <= 'b1;
             'b0000_0001:
                 v <= 'b1;
             default:
                 v <= 'b0;
         endcase
     end
 end

 //---------------------------------------------------------------------------------------------------------------

 wire  [:] condition_a ;

 assign a0  = h_count == 'd2199                   ;  // 3FF
 assign a1  = h_count == 'd0                      ;  // 000
 assign a2  = h_count == 'd1                      ;  // 000
 assign a3  = h_count == 'd2                      ;  // EAV
 assign a4  = h_count >= 'd3 & h_count <= 274     ;  // Blank
 assign a5  = h_count == 'd275                    ;  // 3FF
 assign a6  = h_count == 'd276                    ;  // 000
 assign a7  = h_count == 'd277                    ;  // 000
 assign a8  = h_count == 'd278                    ;  // SAV
 assign a9  = h_count >= 'd279 & h_count <= 2198  ;  // Active

 assign condition_a = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9};

 //---------------------------------------------------------------------------------------------------------------

 reg eav = ;
 reg sav = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
     begin
         video_y <= 'h3FF;
         eav <= 'b0;
         sav <= 'b0;
     end
     else
     begin

         eav <= 'b0;
         sav <= 'b0;

         case(condition_a)
             'b100_0000_000:
                 video_y <= 'h3FF;
             'b010_0000_000:
                 video_y <= 'h000;
             'b001_0000_000:
                 video_y <= 'h000;
             'b000_1000_000:
             begin
                 eav <= 'b1;
                 if( v_count >= & v_count <= )
                     video_y <= {'b1, 1'b0, 'b0, 1'b1, 'b0^1'b1, 'b0^1'b1, 'b0^1'b0, 'b0^1'b0^'b1, 1'b0, 'b0};
                 else
                     video_y <= {'b1, 1'b0, 'b1, 1'b1, 'b1^1'b1, 'b0^1'b1, 'b0^1'b1, 'b0^1'b1^'b1, 1'b0, 'b0};
             end
             'b000_0100_000:
                 video_y <= 'h040;
             'b000_0010_000:
                 video_y <= 'h3FF;
             'b000_0001_000:
                 video_y <= 'h000;
             'b000_0000_100:
                 video_y <= 'h000;
             'b000_0000_010:
             begin
                 sav <= 'b1;
                 if( v_count >=  & v_count <= )
                     video_y <= {'b1, 1'b0, 'b0, 1'b0, 'b0^1'b0, 'b0^1'b0, 'b0^1'b0, 'b0^1'b0^'b0, 1'b0, 'b0};
                 else
                     video_y <= {'b1, 1'b0, 'b1, 1'b0, 'b1^1'b0, 'b0^1'b0, 'b0^1'b1, 'b0^1'b1^'b0, 1'b0, 'b0};
             end
             'b000_0000_001:
                 video_y <= 'h0CD;
             default:
                 video_y <= 'h040;
         endcase
     end
 end

 //---------------------------------------------------------------------------------------------------------------

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         video_c <= 'h3FF;
     else
     begin

         case(condition_a)
             'b100_0000_000:
                 video_c <= 'h3FF;
             'b010_0000_000:
                 video_c <= 'h000;
             'b001_0000_000:
                 video_c <= 'h000;
             'b000_1000_000:
             begin
                 if( v_count >= & v_count <= )
                     video_c <= {'b1, 1'b0, 'b0, 1'b1, 'b0^1'b1, 'b0^1'b1, 'b0^1'b0, 'b0^1'b0^'b1, 1'b0, 'b0};
                 else
                     video_c <= {'b1, 1'b0, 'b1, 1'b1, 'b1^1'b1, 'b0^1'b1, 'b0^1'b1, 'b0^1'b1^'b1, 1'b0, 'b0};
             end
             'b000_0100_000:
                 video_c <= 'h040;
             'b000_0010_000:
                 video_c <= 'h3FF;
             'b000_0001_000:
                 video_c <= 'h000;
             'b000_0000_100:
                 video_c <= 'h000;
             'b000_0000_010:
             begin
                 if( v_count >=  & v_count <= )
                     video_c <= {'b1, 1'b0, 'b0, 1'b0, 'b0^1'b0, 'b0^1'b0, 'b0^1'b0, 'b0^1'b0^'b0, 1'b0, 'b0};
                 else
                     video_c <= {'b1, 1'b0, 'b1, 1'b0, 'b1^1'b0, 'b0^1'b0, 'b0^1'b1, 'b0^1'b1^'b0, 1'b0, 'b0};
             end
             'b000_0000_001:
                 video_c <= 'h0CD;
             default:
                 video_c <= 'h040;
         endcase
     end
 end

 //---------------------------------------------------------------------------------------------------------------

 reg h = ;

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         h <= 'b0;
     else if(h_count ==  | ( h_count >=  & h_count <=  ))
         h <= 'b0;
     else
         h <= 'b1;
 end

 //---------------------------------------------------------------------------------------------------------------

 assign data_enable = h & ~v;

 //---------------------------------------------------------------------------------------------------------------

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         sync_h <= 'b0;
     else if(h_count >=  & h_count <= )
         sync_h <= 'b1;
     else
         sync_h <= 'b0;
 end 

 //---------------------------------------------------------------------------------------------------------------

 always @(posedge clk or posedge rest)
 begin
     if(rest)
         sync_v <= 'b0;
     else if(v_count >= & v_count < )
         sync_v <= 'b1;
     else if(v_count ==  & h_count <=)
         sync_v <= 'b1;
     else
         sync_v <= 'b0;
 end

 //---------------------------------------------------------------------------------------------------------------

 endmodule

 /*

 add_force {/video_source/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
 add_force {/video_source/rest} -radix hex {1 0ns} {0 200ns} 

 */

仿真结果：