mul8_unsigned multipliter

李亚民老师更注重硬件设计思想的训练。
他给出的硬件设计方法更贴近底层硬件，下面看看他的设计思想：
                                                                                                                                   a7a6a5a4a3a2a1a0
                                                                                                                           *       b7b6b5b4b3b2b1b0
                                                                                                                  --------------------------------------------------
                                                                                                                 a7b0  a6b0  a5b0  a4b0  a3b0  a2b0  a1b0  a0b0
                                                                                                      a7b1  a6b1   a5b1  a4b1  a3b1  a2b1  a1b1  a0b1
                                                                                           a7b2  a6b2  a5b2   a4b2   a3b2  a2b2  a1b2  a0b2
                                                                                 a7b3  a6b3  a5b3  a4b3   a3b3   a2b3  a1b3  a0b3
                                                                       a7b4  a6b4  a5b4  a4b4  a3b4   a2b4   a1b4  a0b4
                                                            a7b5  a6b5   a5b5  a4b5  a3b5  a2b5   a1b5   a0b5
                                                 a7b6  a6b6   a5b6   a4b6  a3b6  a2b6  a1b6   a0b6
      +                              a7b7  a6b7  a5b7    a4b7   a3b7  a2b7  a1b7  a0b7
-----------------------------------------------------------------------------------------------------------------------------------------------------------

 //date :2013/6/20
 //designer :pengxiaoen
 //function : unsigned 8 bit  multipliter

 module mul8_unsigned (
                      a_in,b_in,
                             result
                             );
 input [:] a_in, b_in;
 output [:] result ;

 wire [:] ab0 = b_in[] ?  a_in : 'd0;
 wire [:] ab1 = b_in[] ?  a_in : 'd0;
 wire [:] ab2 = b_in[] ?  a_in : 'd0;
 wire [:] ab3 = b_in[] ?  a_in : 'd0;
 wire [:] ab4 = b_in[] ?  a_in : 'd0;
 wire [:] ab5 = b_in[] ?  a_in : 'd0;
 wire [:] ab6 = b_in[] ?  a_in : 'd0;
 wire [:] ab7 = b_in[] ?  a_in : 'd0;

 assign result = ( ({'b0,ab0[7:0]}        +
                    {'b0,ab1[7:0],1'b0})  +
                        ({'b0,ab2[7:0],2'b0}   +
                        {'b0,ab3[7:0],3'b0})  +
                         ({'b0,ab4[7:0],4'b0}   +
                          {'b0,ab5[7:0],5'b0})  +
                         ({'b0,ab6[7:0],6'b0}   +
                          {'b0,ab7[7:0],7'b0})
                     );

 endmodule

这种设计思想很好，但是这个就有点悲剧了

一共用了126个逻辑单元
特权的16bit unsigned multipliter 才用了103个。
吴厚航 PK 李亚民 ，呵呵，不知道怎么样去比较这两个设计思想的优缺点，求指点啊

李老师说如果没有加括号，就也许会顺序执行，但是我加了和么有加么有区别啊