Router pipeline

from

2013-HPCA-Breaking the On-Chip Latency Barrier Using SMART

book_Principles and Practices of Interconnection Networks

Buffer Write (BW): The incoming flit is buffered.
Route Compute (RC): The incoming head flit chooses an output port to depart from.
Switch Allocation (SA): Buffered flits arbitrate among themselves for the crossbar switch.

At the end of this stage, there is at most one winner for every input and output port of the crossbar.

VC Selection (VS): Head flits that win SA reserve a VC for the next router, from a pool of free VCs.
The winners of SA proceed to Switch Traversal (ST) and Link Traversal (LT) to the next router.