ROM的一种写法

module mr_rom_pll_valuemask_8bpc #(
parameter NUMBER_OF_MIF_RANGE = ,
parameter ROM_DEPTH_FOR_EACH_MIF_RANGE = ,
parameter ROM_SIZE = ,
parameter TOTAL_ROM_DEPTH = , // 6*7
parameter ADDR_WIDTH =  // alt_clogb2(42)
) (
input wire clock,
input wire [ADDR_WIDTH-:] addr_ptr,
output wire [ROM_SIZE-:] rdata_out
);

reg [ROM_SIZE-:] ROM [:TOTAL_ROM_DEPTH-];
wire [ROM_SIZE-:] DATAA = {ROM_SIZE{'b0}};
wire [ADDR_WIDTH-:] RADDR;

initial begin
// FIELD_VALMASK
// ROM OFFSET 0 (25MHz - 50MHz)
ROM[] <= 'h00000F0F; // m 30
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000303; // c0 6
ROM[] <= 'h00001E1E; // c1 60
ROM[] <= 'h00001E1E; // c2 60
ROM[] <= 'h00000010; // cp
ROM[] <= 'h00000100; // bw
// ROM OFFSET 1 (51MHz - 70MHz)
ROM[] <= 'h00000A0A; // m 20
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000202; // c0 4
ROM[] <= 'h00001414; // c1 40
ROM[] <= 'h00001414; // c2 40
ROM[] <= 'h0000000B; // cp
ROM[] <= 'h000000C0; // bw
// ROM OFFSET 2 (71MHz - 100MHz)
ROM[] <= 'h00000505; // m 10
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000101; // c0 2
ROM[] <= 'h00000A0A; // c1 20
ROM[] <= 'h00000A0A; // c2 20
ROM[] <= 'h00000010; // cp
ROM[] <= 'h000000C0; // bw
// ROM OFFSET 3 (101MHz - 170MHz)
ROM[] <= 'h00000404; // m 8
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000404; // c0 8
ROM[] <= 'h00000808; // c1 16
ROM[] <= 'h00000808; // c2 16
ROM[] <= 'h00000010; // cp
ROM[] <= 'h000000C0; // bw
// ROM OFFSET 4 (171MHz - 340MHz)
ROM[] <= 'h00000202; // m 4
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000202; // c0 4
ROM[] <= 'h00000404; // c1 8
ROM[] <= 'h00000404; // c2 8
ROM[] <= 'h00000010; // cp
ROM[] <= 'h000000C0; // bw
// ROM OFFSET 5 (85.25MHz - 150MHz) - 2.0
ROM[] <= 'h00000404; // m 8
ROM[] <= 'h00010000; // n 1
ROM[] <= 'h00000101; // c0 2
ROM[] <= 'h00000202; // c1 4
ROM[] <= 'h00000202; // c2 4
ROM[] <= 'h00000010; // cp
ROM[] <= 'h000000C0; // bw
// Set the rest to all zeros
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
ROM[] <= 'h00000000;
end

// write is unused
wire [ADDR_WIDTH-:] ADDRA = {ADDR_WIDTH{'b0}};
wire WEA = 'b0;
always @ (posedge clock)
begin
if (WEA) begin
ROM[ADDRA] <= DATAA;
end
end

assign RADDR = addr_ptr;

reg [ROM_SIZE-:] RDATA;
always @ (posedge clock)
begin
RDATA <= ROM[RADDR];
end

assign rdata_out = RDATA;

endmodule