Quartus prime16.0 组合逻辑always块中敏感向量表不全

前言

组合逻辑always块中向量敏感表不全导致的警告。

流程

1.对于如下代码块：

 always @(nstate /*or master_din or master_dout_reg*/) begin
     //initial;
     master_din_reg = ;
     master_dout = ;
     cs = 'b0;
     wr_done = 'b0;
     rd_done = 'b0;
     sck_en = 'b0;
     case (nstate)
         IDEL: begin
             cs = 'b1;
             wr_done = 'b0;
             rd_done = 'b0;
         end
         LOAD: begin
             cs = 'b0;
             master_din_reg = master_din;
         end
         SEND: begin
             sck_en = 'b1;
         end
         FINISH: begin
             cs = 'b1;
             wr_done = 'b1;
             rd_done = 'b1;
             sck_en = 'b0;
             master_dout = master_dout_reg;
         end
         default: begin
             master_din_reg = ;
             master_dout = ;
             cs = 'b0;
             wr_done = 'b0;
             rd_done = 'b0;
             sck_en = 'b0;
         end
     endcase //case
 end

对于master_din和变量master_dout_reg，两者在组合always块中使用读取，但没有在敏感向量表中，将会导致如下错误：

Warning (10235): Verilog HDL Always Construct warning at spi_ms.v(149): variable "master_din" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at spi_ms.v(159): variable "master_dout_reg" is read inside the Always Construct but isn't in the Always Construct's Event Control

2.解决方法是补全敏感向量表，避免产生不必要的锁存器：

 always @(nstate or master_din or master_dout_reg) begin
     //initial;
     master_din_reg = ;
     master_dout = ;
     cs = 'b0;
     wr_done = 'b0;
     rd_done = 'b0;
     sck_en = 'b0;
     case (nstate)
         IDEL: begin
             cs = 'b1;
             wr_done = 'b0;
             rd_done = 'b0;
         end
         LOAD: begin
             cs = 'b0;
             master_din_reg = master_din;
         end
         SEND: begin
             sck_en = 'b1;
         end
         FINISH: begin
             cs = 'b1;
             wr_done = 'b1;
             rd_done = 'b1;
             sck_en = 'b0;
             master_dout = master_dout_reg;
         end
         default: begin
             master_din_reg = ;
             master_dout = ;
             cs = 'b0;
             wr_done = 'b0;
             rd_done = 'b0;
             sck_en = 'b0;
         end
     endcase //case
 end

3.更懒的方式为直接：always @（*）

解决一切问题。

以上。