44.do文件格式

style1:

transcript on
if {[file exists rtl_work]} {
<span style="white-space:pre"> </span>vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi/pkg_param.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi/pkg_trellis.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi/dec_viterbi.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi/dec_viterbi_tb.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cycloneive -L rtl_work -L work -voptargs="+acc" dec_viterbi_tb

add wave *
view structure
view signals
run -all

//----------------------------------------------------------------------------

style2:

transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi_ver2/pkg_param.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi_ver2/pkg_trellis.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi_ver2/dec_viterbi.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi_ver2/acs.vhd}
vcom -93 -work work {C:/Users/Du/MyWork/WiFi-FPGA/viterbi_ver2/dec_viterbi_tb.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cycloneive -L rtl_work -L work -voptargs="+acc" dec_viterbi_tb

add wave /dec_viterbi_tb/u1/clk_in
add wave /dec_viterbi_tb/u1/clk_out
add wave /dec_viterbi_tb/u1/cnt_dec
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/inrecv
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/inprepm_high
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/inprepm_low
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/v_high
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/v_low
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/outpm
add wave /dec_viterbi_tb/u1/gen_acs__63/inst_acs/outsp

add wave /dec_viterbi_tb/u1/pmm

view structure
view signals
run -all

比较两种style，基本没什么区别，重点是红色tcl部分，它已经包含了几张常用库，如果没这些-L altera_mf等库，就需要自己重新添加仿真库，显得更加复杂；

do文件有很多脚本语言，可以学习更加简单易用的命令控制语句！