004:ZYNQ_AXI总线学习笔记（1）

1.    WHAT IS AXI?

AXI是一种高级可扩展接口，是ARM AMBA的一部分。

2.    WHAT IS AMBA?

AMBA是高级微控制器总线架构，开放的片内互联总线标准。

3．AXI分类

AXI4/AXI4_ITE/AXI4_STREAM

Memory_mapped 存储器映射 就是读写数据时需要目标地址。

AXI4(AXI4_FULL):用于高性能存储映射。例如：AXI4读写DDR3。

AXI4_LITE:简单的，低吞吐率。比如说一些控制寄存器和状态寄存器。

AXI4_STREAM（ST）：高速的流数据通信。

AXI4(AXI4_FULL)和AXI4_LITE需要主机指定读写的地址。AXI4_STREAM（ST）属于流数据，不需要存储器映射不需要地址。

4.存储器映射（Memory_mapped）

主机在对从机进行读写操作时，要先指定一个目标地址（target address），在这个地址对应系统存储空间的地址，表示对该空间进行读写操作。

Memory-Mapped Protocols: In memory-mapped protocols (AXI3, AXI4, and

AXI4-Lite), all transactions involve the concept of transferring a target
address within a

system memory space and data.

AXI_Stream不属于存储器映射。

5.AXI4的优势

AXI的优势

生产力：

灵活性：AXI4（支持突发256）和AXI4_lite（不支持突发，1个数据）都属于存储器映射。AXI_ST不属于存储器映射，突发长度不受限制。

可获得性：

6.what is 互联？

7. five different channels

Both AXI4 and AXI4-Lite interfaces consist of five different channels:

• Read Address Channel

• Write Address Channel

• Read Data Channel

• Write Data Channel

• Write Response Channel

主机发送读地址，从机返回读数据

Data can move in both directions between
the master and slave simultaneously, and data

transfer sizes can vary. The limit in AXI4 is a burst
transaction of up to 256 data transfers.

AXI4-Lite allows only one data transfer per
transaction.

读操作：主机通过读地址通道向从机发出地址和控制，从机通过读数据通道发送读数据。根据突发长度大小返回不同个数的数据。

写操作：主机先通过写地址通道发出地址和控制信号。然后通过写数据通道发出数据，等从机接收到数据会发送response信号。

AXI4:

读写地址分离，支持同时读写。

需要一个单一地址然后进行256个数据突发。

As shown in the preceding figures, AXI4:

• Provides separate data and address connections for
reads and writes, which allows

simultaneous, bidirectional data transfer.

• Requires a single address and then bursts up to 256
words of data.

AXI4_LITE:

单次一个数据，不支持突发传输。

AXI4-Lite is similar to AXI4 with some
exceptions: The most notable exception is that

bursting is not supported.

AXI4-Stream：

单通道传输数据类似AXI4的写数据通道，且写数据大小没有突发限制。

The AXI4-Stream protocol defines a single channel for
transmission of streaming data. The AXI4-Stream channel models the write data channel of AXI4.
Unlike AXI4, AXI4-Stream

interfaces can burst an unlimited amount of data.

只关心数据流，不需要地址。

AXI4-Stream
Protocol: Use the AXI4-Stream protocol for applications that typically

focus on a data-centric and data-flow paradigm where the concept of an address
is not

present or not required. Each AXI4-Stream acts as a single unidirectional
channel with a

handshaking data flow.

Infrastructure
IP: An infrastructure IP is a building block used to help assemble

systems. Infrastructure IP tends to be a generic IP that moves or transforms
data

around the system using general-purpose AXI4 interfaces and does not interpret
data.

Examples of infrastructure IP are:

° AXI Register slices (for pipelining)

° AXI FIFOs (for buffering/clock conversion)

° AXI Interconnect IP and AXI SmartConnect IP (for
connecting memory-mapped IP

together)

° AXI Direct Memory Access (DMA) engines (for memory-mapped
to stream

conversion)

° AXI Performance Monitors and Protocol Checkers
(for analysis and debug)

° AXI Verification IP (for simulation-based
verification and performance analysis)

These IP are useful for connecting IP together into a system, but are not
generally

endpoints for data.

DMA常用于存储器映射和stream数据流的转换。

比如说ddr中存储了你的有效数据需要做fft
fft IP的接口时stream流 ddr的数据是存储器映射，做操作需要DMA做数据转换。

A common
approach is to build systems that combine AXI4-Stream and AXI

memory-mapped IP together. Often a DMA engine can be used to move streams in
and out

of memory.

注意AXI Data width
converter 和 AXI Direct Memory
Access支持的AXI接口协议。

8.AXI SmartConnect IP and AXI
Interconnect IP

两者都用于一些主从设备的互联（存储器映射类型）。在一些情况下, AXI
SmartConnect IP可以提供高带宽的链接以及低延迟。

The Xilinx
LogiCORE IP AXI Interconnect and LogiCORE IP AXI SmartConnect cores both connect
one or more AXI memory-mapped master devices to one or more memory-mapped slave
devices; however, the SmartConnect is more tightly integrated into the Vivado
design environment to automatically configure and adapt to connected AXI master
and slave IP with minimal user intervention. The AXI Interconnect can be used in
all memory-mapped designs. There are certain cases for high bandwidth
application where using a SmartConnect provides better optimization. The AXI
SmartConnect IP delivers the maximum system throughput at low latency by
synthesizing a low area custom interconnect that is optimized for important
interfaces.The AXI Interconnect core IP (axi_interconnect)
connects one or more AXI memory-mapped master devices to one or more
memory-mapped slave devices。

今天先到这里。

参考资料：

IHI0022D

UG1037

正点原子ZYNQ嵌入式教程