利用状态机(FSM)进行简单的uart串口发送数据

module uart_tx(clk,rst_n,key,txd);

input clk;
input rst_n;
input key;
output reg txd;

reg[:] state;
reg[:] bit_timer;
wire[:] tx_data;
assign tx_data='h5a; 

parameter s_idle='d0;
parameter s_start='d1;
parameter s_bit0='d2;
parameter s_bit1='d3;
parameter s_bit2='d4;
parameter s_bit3='d5;
parameter s_bit4='d6;
parameter s_bit5='d7;
parameter s_bit6='d8;
parameter s_bit7='d9;
parameter s_stop='d10;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
         state<=s_idle;
         bit_timer<='d0;
         txd<='b1;
    end
    else
    begin
        case(state)

        s_idle:
        begin
            txd<='b1;
            if(!key)
            state<=s_start;
            else
            state<=state;
        end

        s_start:
        begin
            txd<='b0;
            if(bit_timer=='d5208)
            begin
            state<=s_bit0;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

        s_bit0:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit1;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit1:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit2;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

        s_bit2:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit3;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit3:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit4;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit4:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit5;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit5:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit6;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit6:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_bit7;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_bit7:
        begin
            txd<=tx_data[];
            if(bit_timer=='d5208)
            begin
            state<=s_stop;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

         s_stop:
        begin
            txd<='b1;
            if(bit_timer=='d5208)
            begin
            state<=s_idle;
            bit_timer<='d0;
            end
            else
            begin
            state<=state;
            bit_timer=bit_timer+'d1;
            end
        end

        default:
        begin
        state<=s_idle;
        end

        endcase
    end

end

endmodule