写简单的tb（testbench）文件来测试之前的FSM控制的LED

先上我之前写的状态机控制的led代码led_test.v

   module led_test(clk,led_out);
    input clk;
    output reg[:] led_out;

    initial
    begin
        led_out='b0000;
    end

    reg[:] state='b0000;
    reg[:] timer='d0;

    parameter state_0='b0000;
    parameter state_1='b0001;
    parameter state_2='b0010;
    parameter state_3='b0100;
    parameter state_4='b1000;

    always@(posedge clk)
    begin

      case(state)

       state_0:
        if(timer>='d9999_9999)
           begin
              state<=state_1;
               led_out<=state_1;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

           state_1:
        if(timer>='d9999_9999)
           begin
              state<=state_2;
               led_out<=state_2;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

        state_2:
        if(timer>='d9999_9999)
           begin
              state<=state_3;
               led_out<=state_3;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

    state_3:
        if(timer>='d9999_9999)
           begin
              state<=state_4;
               led_out<=state_4;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

            state_3:
        if(timer>='d9999_9999)
           begin
              state<=state_4;
               led_out<=state_4;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

    state_4:
        if(timer>='d9999_9999)
           begin
              state<=state_0;
               led_out<=state_0;
               timer<='d0;
           end
        else
           begin
                  state<=state;
                  led_out<=led_out;
                  timer=timer+'d1;
           end

           default:
           state<=state_0;

      endcase
    end

endmodule

然后下面是我写的一个简陋的tb文件 led_test_tb.v

`timescale 1ns/1ps
module  led_test_tb();
   reg clk;
   wire[:] led_out;
   led_test a (
      .clk(clk),
      .led_out(led_out)
   );

   initial
    begin
      clk=;
   end

   initial
   begin
        clk=;
        forever
         # clk=~clk;
   end

endmodule

但是今天折腾了半天仍然没有输出正确的波形图，只有激励波形，改天接着修改。下面是初次调出的波形图：

马上要考信号与系统了，我还得滚去复习，还要复习考研，抽空学这个，虽然累，但是乐啊，剩下的仿真波形错误我下次再来改吧。