Verilog经典输入控制/激励信号模板1

reg [:]i;

       always @ ( posedge CLOCK or negedge RESET )
           if( !RESET )
               begin
                   i <= 'd0;
                   Start_Sig <= 'b0;
                   WrData <= 'd0;
               end
             else
                 case( i )

                        :
                        if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                        else begin WrData <= 'd8; Start_Sig <= 1'b1; end

                        :
                        if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                        else begin WrData <= 'd9; Start_Sig <= 1'b1; end

                        :
                        if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                        else begin WrData <= 'd10; Start_Sig <= 1'b1; end 

                        :
                        begin i <= i; end

                  endcase 

 initial
      begin
          RSTn = ; #; RSTn = ;
          CLK = ; forever # CLK = ~CLK;
       end