利用profiler工具提高NC-Verilog仿真效率

大家进行芯片验证时，一般都会遇到仿真速度很慢、效率不高的问题。
目前发现了一个方法可以debug上述问题。即，利用NC的profiler工具。

关于profiler工具，我把文档《Cadence® NC-Verilog® Simulator Help》中的原文贴出来：
The profiler is a tool that measures where CPU time is spent during simulation. Although it was developed primarily to help Cadence R&D diagnose performance bottlenecks in the simulator, some of the information in the output file can help you to identify inefficient HDL coding practices. Once you have determined what code the simulator is spending most of its time running, improving the efficiency of this code will have the greatest effect on simulation performance.
The profiler works by interrupting the simulation at regular intervals (currently 100 times per second) and noting what was executing at that time. It keeps track of the number of “hits” on different activities, which approximates the amount of CPU time spent in these activities.
The profiler is easy to run and has minimal impact on simulation performance and memory usage. To run the profiler, use the -profile command-line option when you invoke the simulator (ncsim). Use +ncprofile if you are running in single-step invocation mode with the ncverilog command.

就是说，NC-Verilog在仿真引擎内集成了一个profiler工具，该工具每秒中断仿真器100次，并在终端记录下来，仿真结束时会生成一个日志文件（ncprof.out）。
日志文件里会列出被中断次数最多的模块、代码行和结构类型，这些信息可以帮助诊断是哪些代码或模块在仿真时耗费了最多的时间。
通过修改这些模块，就能提升仿真效率。而Profiler功能本身，对仿真只产生非常小的影响。

我们通过-profile选项打开上述功能，仿真命令如下：

ncverilog +ncprofile <other_options> 

或者

ncsim –profile snapshot_name <other_options>